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Unformatted text preview: 4-52 Chapter 4—Processor Design Fig 4.16 The 3-Bus SRC Design
C bus 32 31 32 general purpose registers 0 R0 A bus B bus 32 32 R31 IR PC MA Memory bus MD • A-bus is ALU operand 1, B-bus is ALU operand 2, and C-bus is ALU output • Note MA input connected to the B-bus A ALU C B Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan ...
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This note was uploaded on 11/25/2010 for the course ECE 525.412 taught by Professor Charlesb.cameron during the Spring '10 term at Johns Hopkins.
- Spring '10
- Computer Architecture