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Unformatted text preview: 4-4 Chapter 4--Processor Design Fig 4.1 Block Diagram of 1-Bus SRC
CPU Figure 4.11 Control Unit Wait Gra PCin ADD Control signals out
31 32 32-bit general purpose registers R31 A 0 31..0 32 Control unit inputs R0 31 PC 0 Data Path
IR Main memory Input/ output A ALU C C B MA To memory subsystem MD Memory bus Figures 4.2, 4.3 Computer Systems Design and Architecture by V. Heuring and H. Jordan 1997 V. Heuring and H. Jordan 4-10 Chapter 4--Processor Design Fig 4.3 More Complete View of Registers and Buses in the 1-Bus SRC Design, Including Some Control Signals
Figure 4.4 31 R0 32 32-bit general purpose registers 32 CONin 0 31..0 31 PC
D Q 0 CON Cond logic Figure 4.9 Concrete RTN lets us add detail to the data path Instruction register logic and new paths Condition bit flip-flop Shift count register Keep this slide in mind as we discuss concrete RTN of instructions. 1997 V. Heuring and H. Jordan 5 R31 Op
Register select 5 Select logic c32..0 Figure 4.5 IR Select logic A 32 32 A ALU C 4..0 C
Decrement c131..0 c231..0 MA To memory subsystem MD 4 n 0 n=0 Figure 4.8 Shift count, n Figure 4.6 B Figure 4.7 Computer Systems Design and Architecture by V. Heuring and H. Jordan ...
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This note was uploaded on 11/25/2010 for the course ECE 525.412 taught by Professor Charlesb.cameron during the Spring '10 term at Johns Hopkins.
- Spring '10
- Computer Architecture