SRC_RTN_Summary

SRC_RTN_Summary - Reference Materials 1. RTN Description of...

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Unformatted text preview: Reference Materials 1. RTN Description of SRC Unified RTN for SRC Below is the entire RTN description for SRC with reset and exceprion handling in- tegrated into it. Memory Processor state PC 31..0 : program counter (address of the next instruction) IR 31..0 : instruction register Run: one bit run/halt indicator Strt: start and hard reset signal Rst: soft reset signal R[0..31] 31..0 : general purpose registers Processor interrupt mechanism ireq: interrupt request signal iack: interrupt acknowledge signal IE: one bit interrupt enable flag IPC 31..0 : storage for PC saved upon interrupt II 31..0 : interrupt info.: about source of last interrupt Isrc_info 15..0 : information from interrupt source Isrc_vect 7..0 : type code from interrupt source Ivect 31..0 := 20@0#Isrc_vect 7..0 #4@0: Main memory state Mem[0..2 32- 1] 7..0 : 2 32 addressable bytes of memory M[x] 31..0 := Mem[x]#Mem[x+1]#Mem[x+2]#Mem[x+3]: Formats Instruction formats op 4..0 := IR 31..27 : operation code field ra 4..0 := IR 26..22 : target register field rb 4..0 := IR 21..17...
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SRC_RTN_Summary - Reference Materials 1. RTN Description of...

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