Task 2 Files and Timing Diagram

Task 2 Files and Timing Diagram - SEQUENCE.VHD library...

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SEQUENCE.VHD library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity sequence is port( clk : in std_logic; reset : in std_logic; x: in std_logic; z : out std_logic; a : out std_logic; b : out std_logic;
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c : out std_logic; d : out std_logic; e : out std_logic; f : out std_logic; g : out std_logic; h : out std_logic; i : out std_logic); end sequence; architecture behavioral of sequence is -- This is similar to a variable declaration. The variable names are in -- the parenthesis and they are of type 'state_type'. type state_type is (a1, b1, c1, d1, e1, f1, g1, h1, i1); -- Create signals "state" and "next_state". These signals carry 'state_type' -- signals which were declared above. signal state, next_state : state_type; begin -- This is the first of three processes we will define in our sequence -- detector. Here we define reset and state changes occuring on the -- rising edge of a clock signal (clocked synchronous state machine). state_register: process (clk, reset) begin if (reset = '1') then --if reset is high, goto state a1 state <= a1; elsif (clk'event and clk = '1') then --if not, and rising
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state <= next_state; --edge, go to next state end if; end process; -- This second process steps through each state based on state diagram. -- The sequence is "11010010" next_state_func: process (x, state) begin case state is when a1 => if x = '1' then next_state <= b1; else next_state <= a1; end if; when b1 => if x = '1' then next_state <= c1; else next_state <= a1; end if; when c1 => if x = '1' then next_state <= c1; else next_state <= d1; end if; when d1 => if x ='1' then
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next_state <= e1; else next_state <= a1; end if; when e1 => if x = '1' then next_state <= c1; else next_state <= f1; end if; when f1 => if x = '1' then next_state <= b1; else next_state <= g1; end if; when g1 => if x = '1' then next_state <= h1; else next_state <= a1; end if; when h1 => if x = '1' then next_state <= c1; else next_state <= i1; end if; when i1 =>
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if x = '1' then next_state <= b1; else next_state <= a1; end if; end case; end process; -- This process controls the output of the sequence detector. -- Each state has it's own output along with 'z' which indicates -- the entire sequence 10010 has been detected. output_func:
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This note was uploaded on 11/29/2010 for the course CSE 120 taught by Professor Brucecarlton during the Spring '10 term at Mesa CC.

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Task 2 Files and Timing Diagram - SEQUENCE.VHD library...

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