Vince - A Current Folded Down Conversion Mixer in 0.18 CMOS...

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A Current Folded Down Conversion Mixer in 0.18μ CMOS Vincent Karam Project Supervisor Dr. John W. M. Rogers The submission of this report is for partial fulfillment of the requirement for obtaining The Bachelor of Engineering degree Department of Electronics Carleton University Ottawa, Canada April 09, 2003
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A Current Folded Down-Conversion Mixer in 0.18 μ CMOS 2 Acknowledgements I would like to thank my supervisor Dr. John W. M. Rogers for his guidance and intuition as well as my group members for their collaborative efforts and input.
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A Current Folded Down-Conversion Mixer in 0.18 μ CMOS 3 Table of Contents Acknowledgements ......................................................................................................................... 2 Table of Contents ............................................................................................................................ 3 Lists of Figures ................................................................................................................................ 4 List of Tables ................................................................................................................................... 5 Nomenclature .................................................................................................................................. 6 1.0 Introduction ............................................................................................................................... 7 2.0 Background ............................................................................................................................... 8 3.0 Mixer Theory ............................................................................................................................. 9 3.1 Introduction ........................................................................................................................... 9 3.2 Linearity .............................................................................................................................. 10 3.3 Third Order Intercept Point IP3 .......................................................................................... 11 3.4 1dB Compression Point ...................................................................................................... 11 3.5 Spurious Free Dynamic Range (SFDR) .............................................................................. 12 3.7 Noise ................................................................................................................................... 13 3.8 Double Balanced Gilbert Mixer .......................................................................................... 14 4.0 Image Reject Mixer Design ..................................................................................................... 15 4.1 Introduction ......................................................................................................................... 15 4.2 Specifications ...................................................................................................................... 16 4.3 Design Methodology ........................................................................................................... 16 4.4 Folded Mixer Design .......................................................................................................... 18 4.5 Design Procedure ................................................................................................................ 20 4.6 Discussion ........................................................................................................................... 24 5.0 Simulation ............................................................................................................................... 25 5.1 Simulation Results .............................................................................................................. 25 5.2 Mixer Performance Summary ............................................................................................. 32 6.0 Layout ...................................................................................................................................... 33 6.1 Design Issues ....................................................................................................................... 33 6.2 Mixer Core .......................................................................................................................... 36 7.0 Support Circuitry ..................................................................................................................... 40 7.1 Current Sink ........................................................................................................................ 40 8.0 Future Work ............................................................................................................................ 43 9.0 Conclusion ............................................................................................................................... 44 10.0 References ............................................................................................................................. 45
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A Current Folded Down-Conversion Mixer in 0.18 μ CMOS 4 Lists of Figures Figure 1: Integrated Cable Tuner Architecture[1] ........................................................................... 8 Figure 2: Distortion vs. Power Level ............................................................................................ 12 Figure 3: Ideal Double Balanced Mixer ........................................................................................ 14 Figure 4: Hartley Architecture of Image Reject Mixer ................................................................. 15 Figure 5: Standard Gilbert Cell ..................................................................................................... 16 Figure 6: Biasing Mixer Voltages ................................................................................................. 17 Figure 7: Folded Mixed Topology ................................................................................................ 19 Figure 8: Folded Mixer Topology With Optimized Component Values ....................................... 23 Figure 9: Output Buffer Configuration .......................................................................................... 24 Figure 10: Folded Mixer Testbench DC Analysis ......................................................................... 26 Figure 11: Folded Mixer Core DC Analysis ................................................................................. 26 Figure 12: AC Analysis of IF Output Signal ................................................................................. 27 Figure 13: DFT, Output Frequency Spectrum ............................................................................... 28 Figure 14: P1dB Compression Point ............................................................................................. 29 Figure 15: IIP3 Intercept Point ...................................................................................................... 30 Figure 16: Noise Figure ................................................................................................................. 31 Figure 17: Complete Mixer Layout Top View .............................................................................. 35 Figure 18: Driver Stage Layout View ........................................................................................... 36 Figure 19: Switching Stage Layout View ..................................................................................... 37 Figure 20: 2.53K Bias Resistors ................................................................................................. 38 Figure 21: 11K Bias Resistor ..................................................................................................... 39 Figure 22: 3pF Capacitor ............................................................................................................... 39 Figure 23: Top Level View of 4mA and 1mA Current Sinks ....................................................... 40 Figure 24: 1mA Current Sink Schematic View ............................................................................. 41 Figure 25: 1mA Current Sink Layout View .................................................................................. 41 Figure 26: 4mA Current Sink Schematic View ............................................................................. 42 Figure 27: 4mA Current Sink Layout View .................................................................................. 42
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A Current Folded Down-Conversion Mixer in 0.18 μ CMOS 5 List of Tables Table 1: Cable Tuner Project Participants ....................................................................................... 7 Table 2: Down Conversion Mixer Specifications ......................................................................... 16 Table 3: Final Component Values for Folded Mixer .................................................................... 23 Table 4: Simulation Input Variables .............................................................................................. 25 Table 5: PAC and PSS Frequencies .............................................................................................. 30 Table 6: Mixer Performance Summary ......................................................................................... 32
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A Current Folded Down-Conversion Mixer in 0.18 μ CMOS 6 Nomenclature AC Alternating Current C Capacitor CMC Canadian Microelectronic Corporation DC Direct Current dB Decibels dBm Decibels with respect to 1mW DOCSIS Data Over Cable Service Interface Specification DRC Design Rule Check
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