Lecture10 - ECE 124A ECE 124A LSI Principles LSI Principles...

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Unformatted text preview: ECE 124A ECE 124A LSI Principles LSI Principles VLSI Principles VLSI Principles Lecture 10 Lecture 10 CMOS Inverters: Delay, Power and Sizing CMOS Inverters: Delay, Power and Sizing Prof. Kaustav Banerjee Electrical and Computer Engineering E-mail: [email protected] Lecture 10, ECE 124A, VLSI Principles Kaustav Banerjee Propagation Delay Propagation Delay Lecture 10, ECE 124A, VLSI Principles Kaustav Banerjee Two CMOS Inverters… Two CMOS Inverters… V DD PMOS 1.2 m 2 In Out Metal1 =2 Polysilicon GND NMOS Lecture 10, ECE 124A, VLSI Principles Kaustav Banerjee CMOS inverter capacitances CMOS inverter capacitances Vcc Cgs,p Csb,p Cap on Node f: • nction cap d C Vin Cgd,p Cdb,p d db f Junction cap : C db,p and C db,n • Gate (overlap) capacitance C gd,p and C gd,n (beware of Miller effect) Cgd,n Cdb,n Cint Cg • Interconnect cap : C int • Receiver gate cap : C g Cgs,n Csb,n Assumption: Vin is driven by an ideal voltage source….with zero rise and fall times….hence the ansistors are either in cut ff or Lecture 10, ECE 124A, VLSI Principles Kaustav Banerjee Gnd transistors are either in cut off or saturation mode…hence, no channel capacitance MOS inverter capacitances MOS inverter capacitances CMOS inverter capacitances CMOS inverter capacitances gate p gd n gd p db n db load C C C C C C C int , , , , w sw p db n db C PK C AK C C , , , ox D p , gd n , gd C WX C , C 2 ox drawn gate C WL C jsw eqsw j eq For each gate Miller Effect Lecture 10, ECE 124A, VLSI Principles Kaustav Banerjee CMOS Inverter Propagation Delay CMOS Inverter Propagation Delay pproach 1 pproach 1 Approach 1 Approach 1 D V DD t pHL = C L V swing /2 I av V out C L I av C L k n V DD ~ Note: q = C V Lecture 10, ECE 124A, VLSI Principles Kaustav Banerjee V in = V DD CMOS Inverter Propagation Delay CMOS Inverter Propagation Delay pproach 2 pproach 2 Approach 2 Approach 2 V D DD t pHL = f(R on .C L ) 0 69 R V out = 0.69 R on C L R on C L V out V DD 1 ln(0.5) V = V D 0.5 0.36 Lecture 10, ECE 124A, VLSI Principles Kaustav Banerjee in DD t R on C L Transient Response Transient Response ue to C f transistors: directly couples voltage at input to 3 ? Due to C gd of transistors: directly couples voltage at input to output before the transistors can even start to react to changes at the input----can affect gate performance 2 2.5 0 69 C R 2 V in V out Symmetric inverter has t pHL =t pLH 1 1.5 V out (V) t p = 0.69 C L (R eqn +R eqp )/2 t pHL t pLH 0.5 0.5 1 1.5 2 2.5 10-10-0.5 t (sec) ? Lecture 10, ECE 124A, VLSI Principles Kaustav Banerjee x 10 Delay as a function of V Delay as a function of V D DD DD 5 Same as the ON resistance of a transistor…....
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