# Lecture11 - ECE 124A VLSI Principles Lecture 11 Sizing of...

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Lecture 11, ECE 124A, VLSI Principles Kaustav Banerjee ECE 124A VLSI Principles Lecture 11 Sizing of Logical Paths and Networks, Logical Effort Prof. Kaustav Banerjee Electrical and Computer Engineering E-mail: [email protected]

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Lecture 11, ECE 124A, VLSI Principles Kaustav Banerjee Inverter Sizing
Lecture 11, ECE 124A, VLSI Principles Kaustav Banerjee Load capacitances Internal Caps of Driver (Cint): = Junction caps: C db,12 + Gate caps: C gd,12 (including Miller Caps.) External Caps (Cext): = Interconnect cap: C w + Receiver gate caps: C g,43 C L = C int + C ext Vin Vcc Gnd Cgd,12 Cdb,2 Cdb,1 Cw M2 M1 Cg,4 Cg,3 Vout Vout2 M4 M3 Driver Receiver Vcc

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Lecture 11, ECE 124A, VLSI Principles Kaustav Banerjee Inverter Delay • Minimum length devices, L=0.25 μ m • Assume that for W P = 2 W N = 2 W • same pull-up and pull-down currents • approx. equal resistances R N = R P • approx. equal rise t pLH and fall t pHL delays • Analyze as an RC network t pHL = (ln 2) R N C L t pLH = (ln 2) R P C L Delay ( D ): 2 W W Load for the next stage:
Lecture 11, ECE 124A, VLSI Principles Kaustav Banerjee Inverter with Load Load ( C L ) Delay Assumptions: no load zero delay? C L t p = k R W C L R W R W W unit = 1 k is a constant, equal to 0.69

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Lecture 11, ECE 124A, VLSI Principles Kaustav Banerjee Inverter with Load Load Delay C int C ext Delay (t p ) = kR W ( C int + C ext ) = kR W C int + kR W C ext = kR W C int (1+ C ext / C int ) C N = C unit C P = 2 C unit 2 W W t p t p0 C L t p0 (intrinsic delay)
Lecture 11, ECE 124A, VLSI Principles Kaustav Banerjee Intrinsic delay of CMOS inverter Let R eq be the equivalent resistance of the gate (inverter), then delay (t p ) is defined as: t p0 is the intrinsic delay

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Lecture 11, ECE 124A, VLSI Principles Kaustav Banerjee Impact of sizing on gate delay Let S be the sizing factor R ref be the resistance of a reference gate (usually a minimum size gate) C iref be the internal capacitance of the reference gate Hence: 1. Intrinsic delay is independent of gate sizing, and is determined only by technology and inverter layout 2. If S is made very large, gate delay approaches the intrinsic value but increases the area significantly
Lecture 11, ECE 124A, VLSI Principles Kaustav Banerjee Inverter Chain C L If C L is given: - How many stages are needed to minimize the delay? - How to size the inverters? May need some additional constraints. In Out

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Lecture 11, ECE 124A, VLSI Principles Kaustav Banerjee Delay Formula: inverter chain Let C int = γ C gin with γ 1 f = C ext /C gin - effective fanout t p0 relates the input gate cap. and the intrinsic output cap. of the inverter…
Lecture 11, ECE 124A, VLSI Principles Kaustav Banerjee Apply to Inverter Chain C L In Out 1 2 N t p = t p 1 + t p 2 + …+ t pN

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Lecture 11, ECE 124A, VLSI Principles Kaustav Banerjee Optimal Tapering for Given N Delay equation has N - 1 unknowns, C g,2 …. C g,N Minimize the delay, find N - 1 partial derivatives and equate them to zero, or Result: C
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• Fall '08
• York
• Prof. Kaustav Banerjee, Kaustav Banerjee, VLSI Principles, ECE 124A

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