HW2 - ECE 124A, Fall 2010, Hw#2 Prof. Kaustav Banerjee...

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ECE 124A, Fall 2010, Hw#2 Prof. Kaustav Banerjee 1/2 UNIVERSITY OF CALIFORNIA, SANTA BARBARA Department of Electrical and Computer Engineering ECE124A VLSI Principles Last modified on October 1, 2010 Homework #2 Due Date: Oct 8 th by 5:00pm 1. Consider a four-variable expression F(A,B,C,D) given by F = A’BC’D + A’B’C’D’ + A’BCD’ + AB’CD + ABC’D’ + ABCD’ Here A’ represents the complement of A, B’ the complement of B, and so forth. (A) Simplify the expression F into OR-AND-INVERT circuits by using Karnaugh map. (B) Sketch a transistor-level schematic for a single-stage CMOS logic gate for expression F. (C) Sketch a stick diagram for expression F. (D) Estimate the area from the stick diagram. (E) Layout the function F following the stick diagram in (C) using MAX with a minimum size NMOS and PMOS. Capture the screen of your layout and print out as your submission. Your print out should show that no DRC error exists and also labels of VDD , GND , Inputs (A, B, C, D) and Output (F) are needed. (F) Compare the layout size to the estimated area in (D).
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This note was uploaded on 12/04/2010 for the course ECE 134 taught by Professor York during the Fall '08 term at UCSB.

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HW2 - ECE 124A, Fall 2010, Hw#2 Prof. Kaustav Banerjee...

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