HW3 - ECE 124A, Fall 2010, Hw#3 Prof. Kaustav Banerjee...

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ECE 124A, Fall 2010, Hw#3 Prof. Kaustav Banerjee 1/2 UNIVERSITY OF CALIFORNIA, SANTA BARBARA Department of Electrical and Computer Engineering ECE124A VLSI Principles Last modified on October 10, 2010 Homework #3 Due Date: Oct 15 th by 5:00pm 1. Draw the stick diagram of the circuit shown below. Find the Euler path from the corresponding graph for both pull-up and pull-down networks. 2. (a) Use MAX to draw the layout of 2-input static CMOS NOR gate (DO NOT USE SUE). Your layout should be DRC clean. Capture the screen of your layout and print out as your submission. (b) Draw the stick diagram of this NOR gate. (c) Show the detailed processing steps of this NOR gate. 3. (a) Implement the following circuit in Hspice using .SUBCKT command (look into the Hspice manual). Do not use SUE to generate the netlist. Use 65nm technology with VDD =1V and use minimum size transistors for both PMOS and NMOS (size of PMOS should be 2× size of the NMOS). Get the 65 nm bulk model from following link; http://ptm.asu.edu/
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HW3 - ECE 124A, Fall 2010, Hw#3 Prof. Kaustav Banerjee...

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