ECE 124A, Fall 2010, Hw#6
Prof. Kaustav Banerjee
UNIVERSITY OF CALIFORNIA, SANTA BARBARA
Department of Electrical and Computer Engineering
Last modified on November 22, 2010
Due Date: Nov 29
Chapter 6, Sections 6.3, 6.4 and 6.5, Chapter 9, Sections 9.1, 9.2, and 9.3
CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition), Neil H. E. Weste and
David Harris, Addison Wesley, 2011.
VLSI Interconnect Design & Optmimization:
Read this paper from the class website:
and A. Mehrotra,"Analysis of On-Chip Inductance
IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, Vol. 21, No. 8,
Draw the Equivalent circuit of a driver–interconnect–load segment (Use RLC model) for
Find the optimum interconnect length and repeater size for 180 nm technology.
Explain the effect of inductance in interconnect modeling for different technology (180nm,
90nm, 65nm, and 45nm).
Find the optimum interconnect length and buffer size for 180nm technology. Simulate the
circuit using HSPICE for three different input rise time (0.1 ns, 0.5ns, 1ns).
Explain the effect of driver resistance and driver output capacitance on step response of the
What is the relation of the repeater size obtained from RC model to the repeater size obtained
from RLC model (for different inductance)?