HW6 - ECE 124A, Fall 2010, Hw#6 Prof. Kaustav Banerjee...

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ECE 124A, Fall 2010, Hw#6 Prof. Kaustav Banerjee 1 UNIVERSITY OF CALIFORNIA, SANTA BARBARA Department of Electrical and Computer Engineering ECE124A VLSI Principles Last modified on November 22, 2010 Homework #6 Due Date: Nov 29 th by 5:00pm Reading Assignment: Chapter 6, Sections 6.3, 6.4 and 6.5, Chapter 9, Sections 9.1, 9.2, and 9.3 CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition), Neil H. E. Weste and David Harris, Addison Wesley, 2011. . 1. VLSI Interconnect Design & Optmimization: Read this paper from the class website: K. Banerjee and A. Mehrotra,"Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 8, August 2002. i) Draw the Equivalent circuit of a driver–interconnect–load segment (Use RLC model) for interconnect. ii) Find the optimum interconnect length and repeater size for 180 nm technology. iii) Explain the effect of inductance in interconnect modeling for different technology (180nm, 90nm, 65nm, and 45nm). iv) Find the optimum interconnect length and buffer size for 180nm technology. Simulate the circuit using HSPICE for three different input rise time (0.1 ns, 0.5ns, 1ns). v) Explain the effect of driver resistance and driver output capacitance on step response of the circuit. vi) What is the relation of the repeater size obtained from RC model to the repeater size obtained from RLC model (for different inductance)? vii)
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This note was uploaded on 12/04/2010 for the course ECE 134 taught by Professor York during the Fall '08 term at UCSB.

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HW6 - ECE 124A, Fall 2010, Hw#6 Prof. Kaustav Banerjee...

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