HW7 - ECE 124A, Fall 2010, Hw#7 Prof. Kaustav Banerjee...

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ECE 124A, Fall 2010, Hw#7 Prof. Kaustav Banerjee 1 UNIVERSITY OF CALIFORNIA, SANTA BARBARA Department of Electrical and Computer Engineering ECE124A VLSI Principles Last modified on November 28, 2010 Homework #7 Due Date: December 6 by 5:00pm 1. A 1-T DRAM cell as following consists of a single transistor connected in series with a capacitor. For a read, the bit line is precharged to VDD/2 by a clocked precharge circuit. Then, the access transistor is turned on by applying VDD to the word line. A write is performed by applying VDD or GND to the bit line and VDD to the word line. Assume that VT0= 0.4 V, γ = 0.3 V 1/2 , |2 φ F| = 0.6V a) Find the maximum voltage across the storage capacitor Cs after writing a 1 into the memory cell (i.e., bit line is driven to VDD = 2.5V). b) Ignoring leakage currents, find the voltage on the bit line when this “1” is read from the memory cell. 2. The generic SRAM cell as shown below requires 6 transistors per bit. At first, it seems like the margins in such a memory cell should be good, since it contains two CMOS inverters, which
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This note was uploaded on 12/04/2010 for the course ECE 134 taught by Professor York during the Fall '08 term at UCSB.

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HW7 - ECE 124A, Fall 2010, Hw#7 Prof. Kaustav Banerjee...

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