HWSOL1 - POS(X Y(X’ Z’ W(X’ Y’ Z’ BC 5(a P should...

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2. (a) 2. (B) Two approaches: (1) Use the following circuits for implementation of AND/OR gates:
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(2) Read the pass transistor logic design at: ans_comb_vlsi_course.pdf or a similar resource: 3. A 0 1 00 d 0 01 1 1 11 0 d 10 d d F(A,B,C) = B’C Assuming all don’t cares to be zero, gives the minimal function. 4. SOP: X’Y+XY’W+XZ’
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Unformatted text preview: POS: (X+Y)(X’+Z’+W)(X’+Y’+Z’) BC 5. (a) P should cover all minterms in T1 and T2: Pmin= Σ (0,1,2,3,4,5,6,7,11,15) (b) T1 should not have the common minterms of Pmin and T2: T2 should not have the common minterms of Pmin and T1: (c) P must have common minterms of T1 and T2 , so PMax = Σ (3,7,11,15) (d) It is not possible due to conflict that will be generated by using OR and AND gate. 1....
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