HWSOL2 - 1(a F=(A B C D(A B D(A B C D(A B C D(B C D(b 2(a...

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1. (a) F=(A+B+C+D)(A’+B’+D)(A+B’+C+D’)(A’+B+C’+D’)(B’+C’+D) (b)
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2. (a) 00 01 11 10 00 1 01 1 1 11 1 10 1 1 00 01 11 10 00 01 1 11 1 1 10 1 (c) Use the following functions to implement it as a pass transistor logic. V=1 V=0 WX YZ
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3. 00 01 11 10 00 01 1 1 11 1 10 1 1 F=A’BC’+BC’D+AB’C C B A Out 0 0 0 0 0 0 1 0 0 1 0 D 0 1 1 D 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 0 CD AB C B A 0 0 D D 0 1 0 0 F
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4.
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(C) Sol : Tie J and K together to “high” and use CLK of the J-K as input to your T-flip flop. (d) Sol: HSPICE code . include '180nm.txt' .temp 50 *netlist--------------------------------------- Vdd vdd 0 DC 1.8V Vj J 0 DC 1.8V Vk K 0 DC 1.8V Vclk CLK 0 PULSE 0 1.8V 0us 0us 0us 1us 2us *initialization for Q and Q_bar 5/8 .IC V(q)=1.8V V(qbar)=0V * SPICE netlist for "JK" M_1 net_17 Clk Gnd gnd NMOS W=0.18u L=0.18u M_2 net_15 J net_17 gnd NMOS W=0.18u L=0.18u M_3 net_7 qbar Vdd vdd PMOS W=0.18u L=0.18u M_4 net_7 J Vdd vdd PMOS W=0.18u L=0.18u M_5 net_7 Clk Vdd vdd PMOS W=0.18u L=0.18u M_6 net_8 net_1 Gnd gnd NMOS W=0.18u L=0.18u M_7 net_4 net_7 net_8 gnd NMOS W=0.18u L=0.18u M_8 net_4 net_7 Vdd vdd PMOS W=0.18u L=0.18u
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M_9 net_4 net_1 Vdd vdd PMOS W=0.18u L=0.18u
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