Lecture4

Lecture4 - ECE ECE 124A VLSI Principles Lecture 4 Prof....

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ECE 124A LSI Principles VLSI Principles ecture 4 Lecture 4 Prof. Kaustav Banerjee Electrical and Computer Engineering E-mail: kaustav@ece.ucsb.edu @ Lecture 4, ECE 124A, VLSI Principles Kaustav Banerjee
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MOS Process CMOS Process A single-well CMOS…. ote the OCOS ocal Oxidation of Si) process used for isolation of Note the LOCOS (Local Oxidation of Si) process used for isolation of different transistors A problem with LOCOS is…. Bird’s Beak! ...... which can eliminate the ctive areas in caled CMOS technology Lecture 4, ECE 124A, VLSI Principles Kaustav Banerjee active areas…. .in scaled CMOS technology (solution: use STI-shallow trench isolation )
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asic Steps Basic Steps Basic Steps I Si Wafer: Single-crystalline, lightly-doped wafer (6-12 inch diameter) g y, g y p( ) Thickness of at most 1mm Obtained by cutting a single crystal ingot into thin slices An epitaxial layer is grown over the surface of the wafers before device processing A starting p- wafer has a typical resistivity of 25-50 Ohm-cm, which corresponds to a doing level of the order of 10 15 cm -3 efect density must be very low Defect density must be very low Well dopings are of the order of 10 16 to 10 17 cm -3 (this explains the lower doping of the p substrate Crystal orientation: all ICs are manufactured using (100) surface orientation. Why? (fewer imperfections on a (100) surface….gives significantly better Si/SiO 2 interface) Lecture 4, ECE 124A, VLSI Principles Kaustav Banerjee
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Modern CMOS Process A Modern CMOS Process AlCu iO gate-oxide TiSi 2 poly SiO 2 Tungsten p-well n-well + p-epi SiO 2 n+ p+ p Dual Dual-Well Trench Well Trench-Isolated CMOS Process Isolated CMOS Process -- -- llows more precise control of substrate doping llows more precise control of substrate doping Lecture 4, ECE 124A, VLSI Principles Kaustav Banerjee ---- ----allows more precise control of substrate doping allows more precise control of substrate doping
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Basic Steps Basic Steps-II II Photolithography: Applied throughout the manufacturing process each processing step, a certain area of the chip needs to In each processing step, a certain area of the chip needs to be masked out---using an appropriate optical mask Desired processing step can be selectively applied to the remaining regions Needed for a number of processing steps:
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This note was uploaded on 12/04/2010 for the course ECE 134 taught by Professor York during the Fall '08 term at UCSB.

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Lecture4 - ECE ECE 124A VLSI Principles Lecture 4 Prof....

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