Lecture5 - ECE ECE 124A VLSI Principles Lecture 5 Prof...

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Unformatted text preview: ECE ECE 124A VLSI Principles Lecture 5 Prof. Kaustav Banerjee Electrical and Computer Engineering E-mail: [email protected] Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Design Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules) Design rules are also determined based on reliability and manufacturability issues Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee CMOS CMOS Process Layers Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Layers Layers in 0.25 m CMOS process Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Intra Intra-Layer Design Rules Same Potential 0 or 6 10 3 Active 3 2 Select Contact or Via Hole 2 2 Metal2 3 Different Potential 9 Polysilicon 2 Metal1 3 4 2 Well 3 Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Transistor Transistor Layout Transistor 1 3 2 5 Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Vias Vias and Contacts 2 Via 1 1 5 Metal to 1 Active Contact Metal to Poly Contact 3 2 4 2 2 Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Select Select Layer….an interface for generating the mask 2 3 2 1 3 3 Select 2 5 Substrate Well Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee CMOS CMOS Inverter Layout GND In VD D A A’ Out (a) Layout A p-substrate n + A’ n p + Field Oxide (b) Cross-Section along A-A’ Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Layout Layout Editor….MAX Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Design Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um. Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Stick Stick Diagram….see Section 1.5.5 in text V DD In 3 Out Allows quick layout planning & area estimation without detailed layout • Dimensionless layout entities • Only topology is important • Determine height and width of cell by counting number of wire ll tracks and multiplying by wire pitch (width+spacing) • Final layout generated by layout generated by “compaction” program 1 GND Stick diagram of inverter diagram of inverter Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Circuit Circuit Under Design VDD M2 M4 Vin Vout Vout2 VDD M1 M3 Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Its Its Layout View Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Logic Logic Graph A j B X = (C • (A + B)) C A i B A B C GND B i A PDN C X C Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Two Stick Layouts of (C • (A + B)) Two (A B)) C A X = (C • (A + B)) i B A VDD X GND X GND C B A B C VDD uninterrupted diffusion strip Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Consistent Consistent Euler Path An uninterrupted diffusion strip is possible only if there uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once each edge is visited once and only once. X C i B A GND For a single poly strip for every input signal, the Euler single poly strip for every input signal the Euler paths in the PUN and PDN must be consistent (the same) Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Consistent Consistent Euler Path An uninterrupted diffusion strip is possible only if there uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once each edge is visited once and only once. X j C X = (C • (A + B)) (C (A B)) C A i B X B i A ABC C VDD A B j GND For a single poly strip for every input signal, the Euler single poly strip for every input signal the Euler paths in the PUN and PDN must be consistent (the same) Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Logic Logic Graph A B C D X = ((A+B)•(C+D)) C A D B X B A B C D A PDN D X C VDD PUN GND Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Layout Layout A VDD B D C X GND X = ((A+B)•(C+D)) Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Packaging Packaging Requirements Electrical: Low parasitics Mechanical: Reliable and robust Thermal: Efficient heat removal Economical: Cheap Cheap Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Bonding Techniques Bondin Wire Bonding Substrate Die Pad Lead Frame Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Fli Flip-Chip Bonding Die Solder bumps Interconnect layers Substrate Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Package-to-Board Interconnect Packa (a) Through-Hole Mounting (b) Surface Mount Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Package Types Packa Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Package Parameters Packa Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee Multi Multi-Chip Modules Lecture 5, ECE 124A, VLSI Principles Kaustav Banerjee ...
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