Lecture12

Lecture12 - CE 124A CE 124A ECE 124A ECE 124A LSI...

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Unformatted text preview: CE 124A CE 124A ECE 124A ECE 124A LSI Principles LSI Principles VLSI Principles VLSI Principles Lecture 12 Lecture 12 VLSI Interconnects: VLSI Interconnects: Parasitics Parasitics and Delay Modeling and Delay Modeling Prof. Kaustav Banerjee Electrical and Computer Engineering E-mail: kaustav@ece.ucsb.edu Lecture 12, ECE 124A, VLSI Principles Kaustav Banerjee he Wire he Wire The Wire The Wire transmitters receivers schematics physical Lecture 12, ECE 124A, VLSI Principles Kaustav Banerjee p y Interconnect Impact on Chip Interconnect Impact on Chip Lecture 12, ECE 124A, VLSI Principles Kaustav Banerjee Interconnect delay has become the dominant factor determining chip performance.. Wire Vs Gate Delay.. Wire Vs Gate Delay.. 10 1 10 1 RS 99 10 Optimal Interconnect Delay 10 Optimal Interconnect Delay ITRS 99 Delay Time (ns) Delay Time (ns) Global Wires Interconnect delay has become the dominant factor determining chip performance 10-1 Typical Gate Delay 10-1 Typical Gate Delay 60 80 100 120 140 160 180 10-2 Feature Size (nm) 60 80 100 120 140 160 180 10-2 Feature Size (nm) Lecture 12, ECE 124A, VLSI Principles Kaustav Banerjee K. Banerjee et al., Proc. IEEE, May 2001. pact of Interconnect Parasitics pact of Interconnect Parasitics Impact of Interconnect Parasitics Impact of Interconnect Parasitics terconnect parasitics Interconnect parasitics affect performance and power consumption ffect reliability affect reliability lasses of parasitics Classes of parasitics Resistive Capacitive Inductive Lecture 12, ECE 124A, VLSI Principles Kaustav Banerjee Wire Resistance Wire Resistance R = H W L L H Sheet Resistance R o Unit of " /sq" or " / " W R 1 R 2 Lecture 12, ECE 124A, VLSI Principles Kaustav Banerjee Easier to compare wires with different (but uniform) thicknesses Interconnect Resistance Interconnect Resistance Lecture 12, ECE 124A, VLSI Principles Kaustav Banerjee ealing with Resistance ealing with Resistance Dealing with Resistance Dealing with Resistance Selective Technology Scaling Use Better Interconnect Materials reduce average wire-length e.g. copper, silicides More Interconnect Layers duce average wire- ngth reduce average wire length Lecture 12, ECE 124A, VLSI Principles Kaustav Banerjee heet Resistance heet Resistance Sheet Resistance Sheet Resistance Lecture 12, ECE 124A, VLSI Principles Kaustav Banerjee xample: Intel 0 25 micron Process xample: Intel 0 25 micron Process Example: Intel 0.25 micron Process Example: Intel 0.25 micron Process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric Lecture 12, ECE 124A, VLSI Principles Kaustav Banerjee =h/w Interconnect (RC) Delay Interconnect (RC) Delay Interconnect (RC) Delay Interconnect (RC) Delay On-Chip VLSI interconnects can be modeled as RC elements R is the wire resistance = is the resistivity of the metal L is the wire length A is the cross sectional area = wh (w is the width and h is the height of the wire)...
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This note was uploaded on 12/04/2010 for the course ECE 134 taught by Professor York during the Fall '08 term at UCSB.

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Lecture12 - CE 124A CE 124A ECE 124A ECE 124A LSI...

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