Lecture13 - ECE ECE 124A VLSI Principles Lecture 13 Static...

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ECE 124A VLSI Principles Lecture 13 tatic Gates Sizing Design & Analysis of Static Gates Static Gates-I: Sizing, Design, & Analysis of I: Sizing, Design, & Analysis of CMOS Gates Prof. Kaustav Banerjee Electrical and Computer Engineering pg g E-mail: [email protected] Lecture 13, ECE 124A, VLSI Principles Kaustav Banerjee
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Designing Combinational Logic Circuits Lecture 13, ECE 124A, VLSI Principles Kaustav Banerjee
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Static Vs Dynamic Circuits At every point in time (except during the switching Static Circuits transients) each gate output is connected to either V DD or V ss via a low-resistive path. he outputs of the gates ssume t all times e alue The outputs of the gates assume at all times the value of the Boolean function , implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which lies on temporary storage of signal values on the relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. Resulting gate is simpler and faster, but increased Lecture 13, ECE 124A, VLSI Principles Kaustav Banerjee sensitivity to noise….
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Static and Dynamic CMOS Circuit Families Static: Complementary CMOS obustness low power large fan expensive in terms of area and – (robustness, low power, large fan-in expensive in terms of area and performance) Ratioed Logic (pseudo-NMOS, DCVSL) – (simple and fast at the expense of reduced NM and static power) ass ransistor Logic (Transmission Gate) Pass-Transistor Logic (Transmission Gate) -attractive for specific circuits: MUX, XOR-dominated logic such as Adders) Dynamic: good for fast and complex gates, design process is harder due to parasitic effects, leakage puts an upper limit on the operating frequency of the circuit Domino Logic np-CMOS Which style is best? depends on ease of design performance power area and Lecture 13, ECE 124A, VLSI Principles Kaustav Banerjee ……depends on ease of design, performance, power, area and robustness.
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omplementary CMOS Logic Complementary CMOS Logic Full rail-to-rail swing; high noise margins Logic levels not dependent upon the relative device sizes; ratioless Always a path to Vdd or Gnd in steady state; low output impedance xtremely igh input resistance nearly zero Extremely high input resistance ; nearly zero steady-state input current o direct path steady state between power No direct path steady state between power and ground; no static power dissipation Propagation delay function of load Lecture 13, ECE 124A, VLSI Principles Kaustav Banerjee capacitance and resistance of transistors
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tatic Complementary CMOS Static Complementary CMOS V DD In1 In2 PUN PMOS only F(In1,In2,…InN) InN In1 In2 InN PDN NMOS only PUN and PDN are dual logic networks Lecture 13, ECE 124A, VLSI Principles Kaustav Banerjee
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ual Networks Dual Networks Dual networks: parallel onnection in PUN = Example: NAND gate arallel connection in PUN = series connection in PDN, vice-versa parallel B A F If CMOS gate
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