Lecture14

Lecture14 - ECE ECE 124A VLSI Principles Lecture 14 Static...

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ECE 124A VLSI Principles Lecture 14 tatic Gates Pseudo MOS and Pass ransistor ransistor ogic ogic Static Gates Static Gates II: Pseudo II: Pseudo NMOS and Pass NMOS and Pass Transistor Transistor Logic Logic & ynamic Logic Dynamic Logic Prof. Kaustav Banerjee Electrical and Computer Engineering E-mail: kaustav@ece.ucsb.edu Lecture 14, ECE 124A, VLSI Principles Kaustav Banerjee
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atioed Logic Ratioed Logic Lecture 14, ECE 124A, VLSI Principles Kaustav Banerjee
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Ratioed Logic V D V D V D Need N+1 transistors vs 2N for complementary CMOS DD R L Load DD DD V S Resistive Depletion Load PMOS Load V T < 0 PDN In 1 In 2 In F In 1 In 2 In F PDN In 1 In 2 In F SS PDN V SS 3 V SS 3 V SS 3 (a) resistive load (b) depletion load NMOS (c) pseudo-NMOS Goal: to reduce the number of devices over complementary CMOS Note: a depletion mode NMOS is normally ON…an n-type channel connects the source and drain and a negative gate bias is needed to turn it off…. . Lecture 14, ECE 124A, VLSI Principles Kaustav Banerjee ….and gets rid of (almost) the PMOS devices….
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Ratioed Logic: Resistive Load V DD N transistors + Load R L Load Resistive • V OH = V • V OL = R PN eally V hould be as small as Recall a voltage divider circuit…. DN In 1 In F R + R L • Assymetrical response Ideally V OL should be as small as possible. Hence, R L should be large… Only R L involved in t plh , while both R L and R PN involved in t phl …. V SS PDN 2 In 3 • Static power consumption • t pL = 0.69 R L C L V OH “1” NM V IH V IL H NM L Lecture 14, ECE 124A, VLSI Principles Kaustav Banerjee V OL “0”
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ctive Loads V OH “1” NM Active Loads V IH V IL H NM L V DD V DD Depletion MOS V OH =V DD (assuming V OL from revious stage V V OL “0” F F V SS Load PMOS Load V T < 0 previous stage <V tn ) Ideally V OL should be as small as possible. Hence, PMOS device should be minimum sized… In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN V SS V SS depletion load NMOS pseudo-NMOS However, since V OL is not 0 V, (since PUN is always ON) contention between PMOS and the PDN lowers the NM and results in static power issipation Lecture 14, ECE 124A, VLSI Principles Kaustav Banerjee dissipation.
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Pseudo Pseudo-NMOS NMOS V DD ABCD F C L V OH = V DD (similar to complementary CMOS) To Find V L : k n V V Tn  V OL V 2 2 -------------    k p 2 ------ V V Tp 2 = Note: NMOS in linear mode, since ideally e output=0 V (V V V Note: PMOS in saturation mode k p ((-V DD -V Tp ) V DSATp –V 2 DSATp /2) = 0 + V V V T 11 k p k n ------ (assuming that V T V V ) == = SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!! the output=0 V (V ds =V OL < V gs -V tn ) V OL = p / n W p /W n V DSATp Assuming V OL is small relative to gate drive, (V DD -V T ), and V Tp =V Tn Lecture 14, ECE 124A, VLSI Principles Kaustav Banerjee
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seudo MOS VTC Pseudo Pseudo NMOS VTC NMOS VTC 3.0 Sizing of the load device can be used to trade off parameters such as NM, delay, and power…… 0 2.5 /L 4 V OL = R PN + R L R PN 1.5 2.0 ou t [V] W/L p = 4 W/L = 2 0.5 1.0 V p W/L p = 1 /L = 0.25 W/L p = 0.5 0.0 0.5 1.0 1.5 2.0 2.5 0.0 V in [V] W/L p 0.25 A larger pull-up device improves performance but increases static
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This note was uploaded on 12/04/2010 for the course ECE 134 taught by Professor York during the Fall '08 term at UCSB.

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Lecture14 - ECE ECE 124A VLSI Principles Lecture 14 Static...

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