Lecture15

Lecture15 - ECE ECE 124A VLSI Principles Lecture 15 Dynamic CMOS Gates-2 Sequential CMOS Design-1 Prof Kaustav Banerjee Electrical and Computer

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ECE 124A VLSI Principles Lecture 15 ynamic CMOS Gates Dynamic CMOS Gates Dynamic CMOS Gates-2 & equential CMOS Design Sequential CMOS Design Sequential CMOS Design-1 Prof. Kaustav Banerjee lectrical and Computer Engineering Electrical and Computer Engineering E-mail: [email protected] Lecture 15, ECE 124A, VLSI Principles Kaustav Banerjee
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ynamic Gate Dynamic Gate ff precharge evaluate precharge M p Clk Out Out Clk M p on 1 off AB)+C) In 1 In 2 PDN In C L A C ((AB)+C) 3 M e Clk Clk B M e off on “Foot” To avoid ontention at Two phase operation Precharge (Clk = 0) valuate lk = 1) contention at the dynamic node (Out)…. ut = CLK + (AB)+C CLK Lecture 15, ECE 124A, VLSI Principles Kaustav Banerjee Evaluate (Clk = 1) Out = CLK + (AB)+C . CLK
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Issues in Dynamic Design 2: Charge Sharing Clk M p Charge stored originally on C L is redistributed (shared) C L A Out over C L and C A leading to reduced robustness Clk C A C B B=0 M e Output node voltage drops and cannot be recovered ue to the dynamic nature due to the dynamic nature of the circuit. Lecture 15, ECE 124A, VLSI Principles Kaustav Banerjee
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harge Sharing All inputs = 0 during pre-charge Initial conditions: V out (t=0)=V DD and V x (t=0)=0 Charge Sharing case 1) if V out < V Tn V DD 2 possible scenarios: Final value of V X C L V DD C L V t  C a V V V X + = Clk Out M p From charge conservation…. or V V t V C a C L ------- -V V V X == X C L A M a case 2) if V > V B 0 C a M b V OUT and V X then reach the same value…. . rom charge conservation V V C a C a C L + ----------------------    = C b Clk M e From charge conservation…. Lecture 15, ECE 124A, VLSI Principles Kaustav Banerjee Which of these scenarios is valid?
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harge Sharing Charge Sharing V DD Initial conditions: V out (t=0)=V DD and V x (t=0)=0 2 possible scenarios: Clk Out M p V out < V Tn ….case I V out > V Tn ….case II hich of these scenarios is valid? X C L A M a Which of these scenarios is valid? First find the capacitance ratio: C a /C L The boundary condition between the two cases can be B 0 C a M b determined by setting V out = V Tn (in the expression for case II). Hence, Tn DD Tn L a V V V C C C b Clk M e Case I holds when the C a /C L ratio is smaller than the value defined above, otherwise Case II holds. Overall, it is desirable to keep V ut < |V p | ---since the output of dynamic Lecture 15, ECE 124A, VLSI Principles Kaustav Banerjee out Tp gate might be connected to a static inverter---low level of V out will cause static power consumption. Also, V out must not go below V M of the inverter.
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harge Sharing Example Charge Sharing Example C B A Out Dynamic 3-input EXOR gate Clk Out C L =50fF A A B B B C =15fF 15fF a b B C C a C c =15fF C b =15fF C d =10fF c d Clk Lecture 15, ECE 124A, VLSI Principles Kaustav Banerjee Worst case change in Output is obtained by exposing the maximum number of internal capacitances to the output: this happens for ABC or ABC
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olution to Charge Redistribution Solution to Charge Redistribution Clk M p Out M kp Clk A B Clk M e Precharge internal nodes (to V DD
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This note was uploaded on 12/04/2010 for the course ECE 134 taught by Professor York during the Fall '08 term at UCSB.

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Lecture15 - ECE ECE 124A VLSI Principles Lecture 15 Dynamic CMOS Gates-2 Sequential CMOS Design-1 Prof Kaustav Banerjee Electrical and Computer

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