Lecture16

Lecture16 - ECE ECE 124A VLSI Principles Lecture 16...

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CE 124A ECE 124A LSI Principles VLSI Principles ecture 16 Lecture 16 Sequential CMOS Logic Design Prof. Kaustav Banerjee Electrical and Computer Engineering E-mail: kaustav@ece.ucsb.edu @ Lecture 16, ECE 124A, VLSI Principles Kaustav Banerjee
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Designing Sequential Logic Circuits Lecture 16, ECE 124A, VLSI Principles Kaustav Banerjee
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Sequential Logic utputs puts All useful systems require storage of state information…. COMBINATIONAL LOGIC Outputs Inputs Registers Next state QD Current State CLK generic Finite State Machine (FSM) consisting of combinational logic and registers A synchronous system: all registers are controlled by a single global CLK A generic Finite State Machine (FSM) consisting of combinational logic and registers. Output of the FSM = F ( current inputs , current state ) Next State is determined based on current state and current inputs—fed to the input (D) of the registers Lecture 16, ECE 124A, VLSI Principles Kaustav Banerjee At the rising edge of the CLK, D copied to Q (with some delay) Note: There are 2 storage mechanisms: 1) positive feedback and 2) charge storage
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lassification of Memory Elements Classification of Memory Elements Background Memory: large centralized memory core (high density array structures)---SRAMs and DRAMs Foreground Memory: embedded in a logic (individual registers or register banks)— focus of this section Lecture 16, ECE 124A, VLSI Principles Kaustav Banerjee
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Classification of Memory Elements Static Memory: preserves state as long as power is ON built by using positive feedback or regeneration where the circuit onsists of intentional connections between the output and input of a consists of intentional connections between the output and input of a combinational circuit most useful when register will not be updated for extended periods of time (eg., configuration data loaded at power-up time). Condition also holds for most processors that use conditional clocking , (gated CLK) where the CLK is turned off for unused modules---- no guarantee on how frequently the registers will be clocked and static memories are needed to state information. istable element the most popular form Lecture 16, ECE 124A, VLSI Principles Kaustav Banerjee bistable element is the most popular form
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Classification of Memory Elements Dynamic Memory: store data for short (ms) period of time based on the principle of temporary charge storage n parasitic capacitors in MOS devices on parasitic capacitors in MOS devices similar to dynamic logic…. . capacitors need to be refreshed periodically to compensate for charge akage leakage significantly simpler----hence, provide higher performance and lower power dissipation most useful in datapath circuits that require higher performance levels and are periodically clocked Lecture 16, ECE 124A, VLSI Principles Kaustav Banerjee
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aming Conventions Naming Conventions efinitions: Definitions: a latch is a level sensitive device register is an dge iggered storage element a register is an edge-triggered storage element
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This note was uploaded on 12/04/2010 for the course ECE 134 taught by Professor York during the Fall '08 term at UCSB.

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Lecture16 - ECE ECE 124A VLSI Principles Lecture 16...

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