Lecture18

Lecture18 - ECE 124A VLSI Principles Lecture 18 Digital...

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Lecture 18, ECE 124A, VLSI Principles Kaustav Banerjee Prof. Kaustav Banerjee Electrical and Computer Engineering E-mail: kaustav@ece.ucsb.edu ECE 124A VLSI Principles Lecture 18 Digital Operations: Designing Adders, Multipliers, and Shifters
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Lecture 18, ECE 124A, VLSI Principles Kaustav Banerjee A Generic Digital Processor MEMORY DATAPATH CONTROL Input / Output Static, Dynamic Memory Latch, Register Timing, Stability Interconnect Sequential Circuit Today……
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Lecture 18, ECE 124A, VLSI Principles Kaustav Banerjee DATAPATH The core of a digital Processor where all computations are performed Datapath consists Logic Blocks – Combinational Logic Functions (AND, OR, XOR….) Arithmetic Blocks Addition Multiplication Comparison Shift
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Lecture 18, ECE 124A, VLSI Principles Kaustav Banerjee An Intel Microprocessor 9-1 Mux 5-1 Mux 2-1 Mux ck1 CARRYGEN SUMGEN + LU 1000um b s0 s1 g64 sum sumb LU : Logical Unit SUMSEL a to Cache node1 REG Fetzer, Orton, ISSCC’02 Itanium has 6 integer execution units like this Intel Itanium ® Integer Datapath
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Lecture 18, ECE 124A, VLSI Principles Kaustav Banerjee Bit-Sliced Design Register Adder Shifter Multiplexer Bit 0 Bit 32 …… DATA IN DATA OUT Control Design a single bit datapath and repeat for all bits
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Lecture 18, ECE 124A, VLSI Principles Kaustav Banerjee Adders
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Lecture 18, ECE 124A, VLSI Principles Kaustav Banerjee Design an Adder Fundamental Arithmetic Building Block Performance Logic Level Optimization – Optimize Boolean Functions – Carry Lookahead Circuit Level Optimization – Transistor Sizing Power Consumption
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Lecture 18, ECE 124A, VLSI Principles Kaustav Banerjee Half-Adder Implementations Half-Adder X X y y s c X y X y s c s c X y Half-Adder X y Carry SUM
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Lecture 18, ECE 124A, VLSI Principles Kaustav Banerjee Full-Adder HA HA A B C in C out s A B Cout Sum Cin Full adder in in in in in out in in S A B C ABC ABC C AB BC AC
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Lecture 18, ECE 124A, VLSI Principles Kaustav Banerjee Express Sum and Carry Generate (G) = AB Propagate (P) = A B Delete (D) = A B C o = G + PC i S = P C i Truth Table for Full Adder A B C i S C o status 0 0 0 0 0 D 0 0 1 1 0 D 0 1 0 1 0 P 0 1 1 0 1 P 1 0 0 1 0 P 1 0 1 0 1 P 1 1 0 0 1 G 1 1 1 1 1 G
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Lecture 18, ECE 124A, VLSI Principles Kaustav Banerjee Complimentary Static CMOS Full Adder 28 Transistors A B B A C i C i A X V DD V DD A B C i B A B V DD A B C i C i A B A C i B C o V DD S 0 () in i i o in in S A B C ABC C A B C C AB BC AC C 0 S
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Lecture 18, ECE 124A, VLSI Principles Kaustav Banerjee The Ripple-Carry Adder Propagation Delay is proportional to N t carry dominates the propagation delay Worst case delay: linear with the number of bits t d = O( N ) t adder ~ (N-1)t carry + t sum FA A 0 B 0 S 0 FA A 1 B 1 S 1 FA A 2 B 2 S 2 FA A 3 B 3 S 3 C i0 C o0 C o1 C o2 C o3 C i1 C i2 C i3
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Lecture 18, ECE 124A, VLSI Principles Kaustav Banerjee Inverting Property FA A B S C i C o FA A B S C i C o 0 0 ( , , ) ( , , ) ( , , ) ( , , ) i i i i S A B C S A B C C A B C C A B C Inverting all inputs to FA results in inverted values for all outputs
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This note was uploaded on 12/04/2010 for the course ECE 134 taught by Professor York during the Fall '08 term at UCSB.

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Lecture18 - ECE 124A VLSI Principles Lecture 18 Digital...

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