Homework2.10

Homework2.10 - cuit dice as their older series which they...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
ECE 124d/256c Homework 2 Due: Wed Jan 20, 2010 Reading: DSE chapter 3 to chap 4.2: Problems: p. 143: 3.7, 3.9, 3.10 3. Classical 10Mb Ethernet interconnections traverse a coaxial cable with an impedance of 50 and ε 0 =3.5. The basic data rate of an ethernet is 10MHz with rise and fall times of 25nS. (Higher frequencies are filtered out at the transceiver). Ethernet taps (stubs) have non-zero capacitance and inductance. (In fact they have a round trip response delay of 50nS max). A proper cable has mark- ings every 2.5m. Please explain what the markings are for and why they are at 2.5 meter spacings. Hint: consider the effects of passing from a region of no taps to one in which many taps are spaced very closely along the cable. 4. TI introduced a new series of high speed TTL circuits in standard packaging using identical cir-
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: cuit dice as their older series which they claimed had significantly better noise performance. As-suming they made no electrical changes to the chip or 16-pin dip packaging (i.e. same package) --how could they make this (True!) claim? 5. Consider a new chip you have built with output pad drivers that switch in 500pS. If these chips are placed on an (epoxy) circuit board using PGA packages, what is the maximum length of a wire w/o termination in the circuit board? If the board has a ground plane? (Use the default figures in the notes for parameters). For a 2.5V signaling swing, what level of voltage noise is created by the intrinsic inductance of the package?...
View Full Document

This note was uploaded on 12/04/2010 for the course ECE 134 taught by Professor York during the Fall '08 term at UCSB.

Ask a homework question - tutors are online