# Homework4.10 - ECE 124d/256c Homework 4 Due Wed Feb 3 2010...

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ECE 124d/256c Homework 4 Due: Wed Feb. 3, 2010 Reading: DSE Chapter 4 to 4.3.3 1. For a transistor with the geometry below, calculate values for the parasitic capacitances and re- sistances as follows: Cgdo, Cdb, Cg, Cd (sidewall), Rs, Rd. Dark color is contact metal, light col- or is diffusion, white is poly (gate). This size corresponds to a minimum size transistor in your 0.18um technology. Also find the parasitics above for 3x, 5x, and 10x this width. (The goal here is to link basic circuit modeling parasitics to physical models -- building intuition for device geome- try effects.) All measurements are in microns, please assume the following process parameters: n-chan: φ b=0.8, Vt=0.5v, kp=1.8e-4A/V 2 , Vd(sat)=0.4, Cj=1fF/ μ m 2 , mj=0.37, Cjsw=0.24fF/ μ m, mjsw=0.15, tox=4nm, Cgdo=0.8f/ μ m, rsh = 7/sq p-chan: φ b=0.84, Vt=-0.5v, kp=-3.6e-5A/V 2 , Vd(sat)=-1.5, Cj=1.2fF/ μ m 2 , mj=0.41, Cjsw=0.19fF/ μ m, mjsw=0.35, tox=4nm, Cgdo=0.65f/ μ m, rsh = 7/sq 2. Build similar models to problem 1 above for matrix transistors with the following specifica- tions: (10um,3 gate fingers), (50um, 7 fingers). In addition to the parameters from problem 1, you

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