# Homework6.10 - ECE 124d Homework 6 Due Wed Feb 17 2010...

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• jayrapkc
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ECE 124d Homework 6 Due: Wed Feb. 17, 2010 Reading: DSE chapter 5 (you may skip 5.2): a. inductive power noise b. logic power profile c. on-chip bypass d. symbiotic bypass Read “Decoupling References” and “Symbiotic Bypass Estimation” on line Problems: p. 256, 5.1 (check your model with spice), 5.2, 5.11a, 5.12, 5.13, 5.15 7. Consider a small processor with a 2.5V, 80-bit DDR communication bus operating at 366MHz (1.0 nS rise and fall times). a. If this bus is driving 60 lines on a PC-board, what is the worst case dI/dt if all lines switch at
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Unformatted text preview: once? b. Assuming that the power to drive the board comes from off chip, what is the maximum allow-able inductance of the power and ground supplies to the chip to limit the voltage drop and ground bounce to 0.25V? How many power/ground bumps will this require at 0.5 nH/bump? c. Assuming activity on the bus 15% of the time on average, with source termination (i.e. no DC power) estimate the average power to drive the DDR bus....
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• Fall '08
• York
• Power, Symbiotic Bypass Estimation, d. symbiotic bypass, c. on-chip bypass, DDR communication bus

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