Homework7.10 - low For your estimation(0.18um technology...

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ECE 124d Homework 7 Due: Wed Feb 24, 2010 Reading: Finish Chapter 5 Start Chapter 6 “Noise” 1. A common practice in standard cell design is to fill vacant cell sites with supply bypass circuits that help to support the power rails and lower the power coupled noise in large CMOS designs. Before such designs became prevalent, inverters of various sizes were used for the same purpose. In this problem, you are to estimate the source and drain areas and perimeters for buffers of vary- ing widths for 1x, 2x, 4x, 8x, 16x, 32x sizes. In a typical standard cell library, the choice 1x width is made as a tradeoff of performance, area and achieveable routing density. Transistors of wide widths are laid out as arrays of smaller widths in parallel, sharing sources and drains as shown be-
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Unformatted text preview: low. For your estimation (0.18um technology), use gate widths of 0.18um, clearance to source or drain from gate 0.20um, minimum drain/source width of 0.5um and a 1x n-channel width of 0.45um. Choose a p-channel width to balance the peak Id for rise and fall. Then build spice decks for inverters in the above sizes, estimating source and drain area and pe-rimeter values for transistors built as shown above, given aspect ratios not too far from 1. Finally instrument the decks so that you can measure the capacitance connected to the power rails -- hint: measure the current into the power rail when you try to change its potential. .. Check your capacitance estimate with that from the Sani Nassif bypass paper. p. 298 6.1, 6.2, 6.3, 6.7 S D S D G...
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  • Fall '08
  • York
  • Standard cell, Sani Nassif, minimum drain/source width, supply bypass circuits, Sani Nassif bypass, vacant cell sites

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