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Unformatted text preview: low. For your estimation (0.18um technology), use gate widths of 0.18um, clearance to source or drain from gate 0.20um, minimum drain/source width of 0.5um and a 1x n-channel width of 0.45um. Choose a p-channel width to balance the peak Id for rise and fall. Then build spice decks for inverters in the above sizes, estimating source and drain area and pe-rimeter values for transistors built as shown above, given aspect ratios not too far from 1. Finally instrument the decks so that you can measure the capacitance connected to the power rails -- hint: measure the current into the power rail when you try to change its potential. .. Check your capacitance estimate with that from the Sani Nassif bypass paper. p. 298 6.1, 6.2, 6.3, 6.7 S D S D G...
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- Fall '08