quiz3 - ECE124d/ECE256c Quiz 3 1=1.0mm RW = 3250:mm A CW =...

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Unformatted text preview: ECE124d/ECE256c Quiz 3 1=1.0mm RW = 3250/:mm A CW = 190iF/mm RINV : IlKQ/h CLINV = 7fF*h+5iF Consider the net extracted from a chip design above. The chip has already been routed, but final buffer insertion (adding buffers to speedup the wires) has not been completed. Gate drive capabil- itics have been sealed in terms of a minimum inverter whose RC characteristics are shown in the picture. (h=16 here in the gate indicates that its drive capability is 16x that of a minimum inverter, as well as the parasitic input capacitance, the output capacitance can be neglected). Usea Pi-model for the distribued lines. a. Estimate the delay time for the net from the driver (D) to points A, B. ”TA zmdmz mm «Ht-(2%)» Mi 2 $226 I’Sl TB 2 T». + dogma Hot-{\itw‘totfiabot‘] figflrfi b. The delay found in part a was too long. Assuming a single inverter is added at point A, find the inverter size 71 to minimize the delay to point B. What is the delay to B for this case? 6i“ at *1 76 L: , _ 66 66' lites 01;. ”a, l I I I ”j; I I TX: [weer {132+1t+§)+16«<gt+1t+;)mtaiwwym Tb, : [(fl 410?}(240 +lagsl1t~§ flojlzyo]; my" av 14 . , 5'— M-‘r‘BZ TA+T3 ”2 " n 44t+Lfi+w§ "MKWTHW TAlTB 5' ‘ h ...
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