COE328Final%202008

COE328Final%202008 - COE‐328 Final Exam 2008 1. Design a...

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Unformatted text preview: COE‐328 Final Exam 2008 1. Design a comparator that compares a 4‐bit number A to a 4‐bit number B and gives an Output F=1 if A is not equal B. You must use 2‐input LUTs only. 2. Given the following logic circuit, clock signal, and input waveforms: a) Derive the state‐assigned table b) Sketch the waveforms for Q1, Q2, Y1, and Y2 in the space provided. Note: Assume zero delay for all gates and flip‐flops. Figure 1 ∙ Q2 Q1 0 0 0 1 1 0 1 1 X=0 Y2 Y1 1 1 1 0 1 1 1 1 X=1 Y2 Y1 1 1 1 1 0 1 0 1 CLK /CLR X Q1 Q2 Y1 Y2 0 15 30 45 60 75 90 105 120 135 150 165 180 195 Time (ns) Figure 2 3. Given the following logic circuit, derive its state ta ble and state diagram. If the following sequence 1010110101 is applied to the x input of the c ircuit with the initial sate 01, determine the resulting output sequence on z output. ⊕ Q2 Q1 0 0 0 1 1 0 1 1 Reset 0/0 S0 1/1 1/0 1/0 0/1 S1 0/0 S x z=y2 S1 1 0 S0 0 0 S0 1 1 S2 0 1 S3 1 1 S3 1 1 S3 0 0 S1 1 0 S0 0 0 S0 1 1 w = 11 S3 0/1 x=0 y2 y1 0 0 1 0 1 1 0 1 x=1 y2 y1 1 0 0 0 0 1 1 1 ⊕ x=0 z 0 1 1 0 1 0 0 1 x=1 S2 1/1 4. The state diagram for a finite state machine (FSM) with one input w and two outputs z2 and z1 is given below w=0 A/01 B/10 w=0 w=0 w=1 w=1 D/00 w=0 w=1 w=1 C/00 a) Does the above state diagram use a Moore or Mealy-type model to represent the FSM? Explain your answer. The state diagram represents Moore‐type FSM, since outputs are completely defined by states and do not depend on inputs. b) What is the minimum number of state variables required to represent the states? Explain your answer. Two state variables are required, because 22 = 4, where 4 is the number of states. c) Using the state assignment: A=00, B=01, C=11, and D=10, develop the next state and output equations for implementing the FSM. A B C D Q2 Q1 0 0 0 1 1 1 1 0 w=0 D2 D1 0 1 0 0 0 1 0 0 w=1 D2 D1 1 1 1 0 0 1 0 0 z2 z1 0 1 1 0 0 0 0 0 D2 w \ Q2Q1 0 1 0 0 0 1 0 1 0 1 1 1 0 0 1 0 0 0 w \ Q2Q1 0 1 0 0 1 1 0 1 0 0 D1 1 1 1 1 1 0 0 0 z2 Q2 \ Q1 0 1 0 0 0 1 1 0 Q2 \ Q1 0 1 0 1 0 z1 1 0 0 5. Assuming that an 8 x 4‐bit EPROM is available, explain how the FSM can be implemented with the state assignment in Part C. Fill in the contents of the EPROM in the table below and clearly explain what the addresses and contents of the EPROM represent. Content D2 D1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 Address w A2 A1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 D3 0 1 0 0 0 1 0 0 w A0 A1 D0 0 0 0 0 1 1 0 0 EEPROM D0 D1 D2 D3 D2 D1 D0 Q0 D1 Q1 Q2 Q1 z1 z2 FF A B C D Q2 Q1 0 0 0 1 1 1 1 0 w=0 D2 D1 0 1 0 0 0 1 0 0 w=1 D2 D1 1 1 1 0 0 1 0 0 z2 z1 0 1 1 0 0 0 0 0 6. Which circuit does the following VHDL code represent? LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY system IS PORT (Clock, Reset : IN STD_logic; z : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END system; ARCHITECTURE Behavior OF system IS TYPE State_type IS (A,B,C); SIGNAL y: State_type; BEGIN PROCESS (Reset, Clock) BEGIN IF Reset='0' THEN y<=A; ELSIF(Clock'EVENT AND Clock='1') THEN CASE y IS WHEN A=> THEN y<=B; WHEN B=> THEN y<=C; WHEN C=> THEN y<=A; END CASE; END IF; END PROCESS; PROCESS(y) BEGIN CASE y IS WHEN A=> z <= ''110''; WHEN B=> z <= ''101''; WHEN C=> z <= ''011''; END CASE; END PROCESS; END Behavior; Reset A/ 11 B/ 10 Clk Reset Mod 3 Counter Q2 Q1 Q0 C/ 01 7. This question deals with the processor in LAB7 (See also the Appendix) a) The switches (SW) are set to 0110; carry bit (C) equals to 1, program counter (PC) equals to 1010, accumulator (ACCA) equals to 0110, Random Access Memory location 1010 (RAM (A)) contains 1111 and program memory location 1010 (EPROM3 (A)) contains DA hex. What are the contents of PC, ACCA, C, and RAM (A) after the execution of the current instruction? PC=1010 ACCA=0110 C=1 RAM(A)=1111 SW=0110 EPROM(A)=DA=1101 1010 PC=1010 ACCA=0110 C=1 RAM(A)=1111 b) Write a program (not to exceed 16 instructions) for the processor of LAB7 to search the content of memory locations 3 and 4 for a specific number that is specified by the switches. If the number is found in memory location 3 or 4, display the exact memory location that the number is stored at. Display 0 if the number is not found in memory location 3 or 4. (Use comments with each instruction to explain your program). 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LDAA 3 JEQ 6 LDAA 4 JEQ 11 CLRA JMP 5 CLRA SEC ROLA ROLA JMP 10 CLRA INCA ROLA ROLA JMP 15 ; A=M(3) ; SW=M(3) ; A=M(4) ; SW=M(11) ; SW Not = M(3) or M(4) ; display 0 ; A=0 ; C=1 ; A=1 ; A=3 ; display 3 ; A=0 ; A=1 ; A=2 ; A=4 ; display 4 c) In the “Processor Instruction Set” list above, it is desired to change the STSW N instruction to the STEQ N instruction. The STEQ N instruction would compare contents of the accumulator to data from the switches. If they equal to each other, the data in the accumulator would be inverted and stored into memory location N. Otherwise, control would be transferred to the next instruction in the program storage. Fill in the table for the STEQ N instruction shown below. EPROMs 1&2 Address Lines EPROM1 PAL ACCA ALU181 NCC L1 L0 M S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0 EPROM2 Data Path 161 EPROM /ASWRSM /PECNTA1+A0+ D7 D6 D5 D4 D3 D2 D1 D0 EPROM3 JP N0 OP Code MCode A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0101100 0101101 0 10 0 11 1 1 0000110 00XXXXX X1 X1 0 0 11 11 0 1 0 0 1 0 STEQ N 1 1 1 1 0101100 0101101 0 10 0 11 1 1 0000110 1110000 X1 X0 0 1 11 01 0 1 0 0 1 0 STEQ N Appendix The processor below is the one used in project 7. It use s an ALU whose functions are listed on the following page. The processor instruction set is also given on the following page. Shi ft Register Operating Modes L1 Mode Hold Shift Righ t Shift Left Parallel L oad 0 0 1 1 L0 0 1 0 1 ...
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