19-Final-Code-Generation - CS143 Summer 2008 Handout 19...

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CS143 Handout 19 Summer 2008 August 01, 2008 Final Code Generation Handout written by Maggie Johnson and revised by Julie Zelenski and Jerry Cain. The last phase of the compiler to run is the final code generator. Given an intermediate representation of the source program, it produces as output an equivalent program in the target's machine language. This step can range from trivial to complex, depending how high or low-level the intermediate representation is and what information it contains about the target machine and runtime environment. How aggressively optimized the final result is also makes a big difference. Unlike all our previous tasks, this one is very machine-specific, since each architecture has its own set of instructions and peculiarities that must be respected. The ABI or application binary interface specifies the rules for executable programs on an architecture (instructions, register usage, calling conventions, instruction scheduling, memory organization, executable format, and so on) and these details direct the code generation. The final code generator handles locations of variables and temporaries and generates all the code to maintain the runtime environment, set up and return from function calls, manage the stack and so on. MIPS R2000/R3000 assembly The target language for Decaf is MIPS R2000/R3000 assembly. We chose this because it allows us to use SPIM, an excellent simulator for the MIPS processor. The SPIM simulator reads MIPS assembly instructions from a file and executes them on a virtual MIPS machine. It was written by James Larus of the University of Wisconsin, and gracefully distributed for non-commercial use free of charge. (By the way, SPIM is "MIPS" backwards. Funny. ) There are some links to some excellent SPIM documentation and resources on our class web site that provide more detail on using this tool. You will definitely want to check those out during your last programming project. First, let’s start by looking at the MIPS R2000/R3000 machine. The processor chip contains a main CPU and a couple of co-processors, one for floating point operations and another for memory management. The word size is 32 bits, and the processor has 32 word-sized registers on-board, some of which have designed special uses, others are general-purpose. It also provides for up to 128K of high-speed cache, half each for instructions and data (although this is not simulated in SPIM). All processor instructions are encoded in a single 32-bit word format. All data operations are register to register; the only memory references are pure load/store operations.
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2 Here are the 32 MIPS registers identified by their symbolic name and the purpose each is used for: zero holds constant 0 (used surprising often, so a dedicated register for it) at reserved for assembler v0-v1 used to return results of functions a0-a3 usually used to pass first 4 args to function call (although Decaf places all arguments on the stack) t0-t7 general purpose (caller-saved ) s0-s7 general purpose (callee-saved) t8-t9 general purpose (caller-saved) k0-k1
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  • Fall '09
  • Call stack, MIPS architecture, FP, SPIM, SPIM Simulator

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