SR Latch - EECS
314
Lecture
notes

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Unformatted text preview: EECS
314
Lecture
notes

 ©
2009
A.
Ganago
 Set‐Reset
(SR)
Latch:
 CombinaCon
of
logic
gates
 that
acts
as
a
1‐bit
 memory
cell
 Here
we
consider
normal
operaCon
of
the
latch:
 The
two
inputs
–
Set
(S)
and
Reset
(R)
–

 never
equal
“1”
at
the
same
Cme
 ©
2009
A.
Ganago
 SR
Latch
 1
 A
Logic
Gate
does
not
have
memory
 •  The
Logic
Gate
output
is
enCrely
determined
 by
its
inputs
at
the
parCcular
moment
of
Cme
 (for
example,
described
in
a
Truth
table)
 •  When
we
look
up
the
Truth
table,
we
do
not
 worry
about
what
happened
with
the
system
 in
the
past
 •  Events
of
the
past
do
not
influence
how
the
 Logic
Gate
responds
to
the
present
inputs.
 ©
2009
A.
Ganago
 SR
Latch
 2
 CombinaCons
of
Logic
Gates
can
 have
memory
 •  However,
a
combinaCon
of
two
NOR
gates
can
 act
as
a
1‐bit
storage
device
 •  It
is
the
simplest
“Latch”,
called
Set‐Reset
(SR)

 •  Other
latches
can
be
built
with
NAND
gates
 •  More
advanced
latches
exist,
for
example,
 those
whose
operaCon
is
linked
to
parCcular
 Cming
sequences
dictated
by
the
clock
pulses.


 ©
2009
A.
Ganago
 SR
Latch
 3
 NOR Gate
and
its
Truth
table
 Input Input Output B 0 0 1 1 C 1 0 0 0 4
 NOR A B ©
2009
A.
Ganago
 A 0 1 0 1 SR
Latch
 C SR
Latch:
Block
Diagram
 Reset Q Set
(S)
and
 Reset
(R)
are
 the
inputs.
 Q
and
Q‐bar
 are
the
 outputs.
 5
 SR
Latch:
AlternaCve
Block
Diagram
 Set
(S)
and
 Reset
(R)
are
 the
inputs.
 Q
and
Q‐bar
 are
the
 outputs.
 SR
Latch
 6
 Reset Set Q Q Set ©
2009
A.
Ganago
 Q SR
Latch
 ©
2009
A.
Ganago
 SR
Latch

 1
 EECS
314
Lecture
notes

 ©
2009
A.
Ganago
 SR
Latch:
OperaCon
 •  In
the
SR
latch,
the
output
of
one
NOR
gate
is
 fed
into
the
other
NOR
gate
as
input
thus
it
 becomes
very
important
to
follow
the
cause‐ and‐effect
relaConships
of
signals
 •  In
many
real
circuits,
the
signals
are
fed
into
 gates
of
MOSFETs
that
act
as
capacitors
that
 need
Cme
to
go
from
LOW
to
HIGH
voltage
 •  Thus
we
show
delays
on
Cming
diagrams

 •  Let
us
begin
with
a
single
NOR
gate

 ©
2009
A.
Ganago
 SR
Latch
 7
 Cause‐and‐Effect
in
NOR
gate
(1)
 A B C A ”1”
 “0”
 B ”1”
 “0”
 *
 Time
 Example
 ”1”
 C 1
 “0”
 ©
2009
A.
Ganago
 SR
Latch
 8
 Cause‐and‐Effect
in
NOR
gate
(2)
 •  In
example
1,
both
inputs
A
and
B
were
 originally
“0”
thus
the
output
C
was
“1”
 •  When
A
changed
from
“0”
to
“1”,
the
output
 changed
from
“1”
to
“0”

 •  Note
the
delay
from
the
change
in
the
input
to
 the
change
in
the
output
(see:
curved
arrow)

 •  The
following
change
of
B
from
“0”
to

 “1”
(labeled
*)
made
no
effect
on
the
output

 ©
2009
A.
Ganago
 SR
Latch
 9
 Cause‐and‐Effect
in
NOR
gate
(3)
 A B C A ”1”
 “0”
 B ”1”
 “0”
 Example
 ”1”
 C 2
 “0”
 ©
2009
A.
Ganago
 SR
Latch
 Time
 10
 Cause‐and‐Effect
in
NOR
gate
(4)
 •  In
example
2,
iniCally,
the
inputs
A
=
B
=
“0”
 thus
C
=
“1”
 •  A
changed
from
“0”
to
“1”
but
only
for
a
short
 Cme;
then
it
remained
to
“0”.
As
a
result,
C
 changed
from
“1”
to
“0”
and
remained
to
“1”.

 •  Then
B
changed
from
“0”
to
“1”,
which
drove
 C
from
“1”
to
“0”
 •  Note
the
delay
in
each
change
of
the
output
in
 response
to
the
input
(see:
curved
arrows)

 ©
2009
A.
Ganago
 SR
Latch
 11
 Cause‐and‐Effect
in
NOR
gate
(5)
 •  As
stated
above,
the
NOR
gate
by
itself
does
 not
have
memory:
as
soon
as
the
input
 changes
back,
the
output
follows
 •  Some
of
the
input
signals’
changes
do
not
 have
any
effect
on
the
output
(see
the
 transiCon
labeled
*
in
Example
1)
 •  If
one
input
is
“1”,
the
output
remains
“0”
 regardless
of
the
other
input
 ©
2009
A.
Ganago
 SR
Latch
 12
 SR
Latch

 2
 EECS
314
Lecture
notes

 ©
2009
A.
Ganago
 Cause‐and‐Effect
in
SR
Latch
(1)
 ”1”
 “0”
 ”1”
 R “0”
 Q ”1”
 Example
 “0”
 ”1”
 3
 Q “0”
 S ©
2009
A.
Ganago
 SR
Latch
 Cause‐and‐Effect
in
SR
Latch
(2)
 •  In
Example
3,
iniCally,
inputs
S
=
R
=
“0”;
the
 outputs
are
Q
=
“0”
and
Q‐bar
=
“1”
 •  When
S
goes
to
“1”,
it
drives
Q‐bar
to
“0”
(see
 the
downward
cause‐and‐effect
arrow)
 •  Q‐bar
is
the
input
of
the
second
NOR
gate;
 thus,
when
Q‐bar
=
“0”
(and
R
=
“0”),
its
 output
Q
is
driven
to
“1”
(see
the
upward
 cause‐and‐effect
arrow)
 Time
 13
 ©
2009
A.
Ganago
 SR
Latch
 14
 Cause‐and‐Effect
in
SR
Latch
(3)
 •  In
Example
3,
when
S
=
“1”
and
R
=
“0”,
the
 outputs
are
Q
=
“1”
and
Q‐bar
=
“0”
 •  When
S
returns
from
“1”
to
“0”,
it
does
not
 have
any
effect
on
the
outputs,
because,
if
one
 input
of
a
NOR
gate
is
“1”,
its
output
is
“0”
 regardless
of
the
other
input
 •  Eventually,
inputs
S
=
R
=
“0”;
the
outputs
are
 Q
=
“1”
and
Q‐bar
=
“0”
 ©
2009
A.
Ganago
 SR
Latch
 15
 Cause‐and‐Effect
in
SR
Latch
(4)
 •  In
Example
3,
the
final
state
of
the
latch
is
 disCnct
from
the
iniCal
state
 •  IniCally,
inputs
are
S
=
R
=
“0”;
the
outputs
are
 Q
=
“0”
and
Q‐bar
=
“1”
 •  Finally,
inputs
are
S
=
R
=
“0”;

but
the
outputs
 are
Q
=
“1”
and
Q‐bar
=
“0”
 •  The
outputs
“remember”
that
S
used
to
be
“1”
 •  This
is
memory
funcCon
 ©
2009
A.
Ganago
 SR
Latch
 16
 Cause‐and‐Effect
in
SR
Latch
(5)
 ”1”
 “0”
 ”1”
 R “0”
 Q ”1”
 Example
 “0”
 ”1”
 Q 4
 “0”
 S ©
2009
A.
Ganago
 SR
Latch
 Cause‐and‐Effect
in
SR
Latch
(6)
 •  The
sequence
of
events
shown
in
Example
3
is
 repeated
in
the
beginning
of
Example
4

 •  Then,
Example
4
shows
what
happens
when
 input
R
goes
from
“0”
to
“1”
and
back
to
“0”
 •  When
R
changes
from
“0”
to
“1”
it
drives
Q
to
 “0”
(see
the
first
downward
arrow)
 •  The
change
of
Q
from
“1”
to
“0”
drives
Q‐bar
 to
“1”
(see
the
second
downward
arrow)
 ©
2009
A.
Ganago
 SR
Latch
 18
 first
 second
 Time
 17
 SR
Latch

 3 EECS
314
Lecture
notes

 ©
2009
A.
Ganago
 Cause‐and‐Effect
in
SR
Latch
(7)
 •  Note
that,
at
the
end
of
Example
4,
when
 input
R
goes
from
“1”
back
to
“0”,
the
state
of
 the
outputs
remains
unchanged
 •  At
the
end
of
Example
4,
the
iniCal
state
of
the
 SR
latch
is
fully
restored
 •  The
memory
wrihen
(Set)
by
S,
has
been
 erased
(Reset)
by
R
 ApplicaCon
of
SR
Latch
(1):
 How
you
call
for
a
Flight
Ahendant

 Reset
(R)
 is
the
 buhon
in

 the
flight
 ahendant
 cabin
 ©
2009
A.
Ganago
 LED
 Set
(S)
is
the
call
buhon
 at
the
passenger
seat

 SR
Latch
 20
 ©
2009
A.
Ganago
 SR
Latch
 19
 ApplicaCon
of
SR
Latch
(2)
 •  S
is
the
input
that
you
change
from
“0”
to
“1”
 when
you
press
the
buhon
to
call
a
flight
 ahendant
 •  Q
is
the
output
that
turns
on
the
LED
to
show
 the
flight
ahendant
that
you
called
for
help
 •  Note
that
–
thanks
to
the
memory
funcCon
–
 the
LED
remains
on
aier
you
briefly
pressed
 the
S
buhon

 ©
2009
A.
Ganago
 SR
Latch
 21
 ApplicaCon
of
SR
Latch
(3)
 •  R
is
the
input
that
a
flight
ahendant
changes
 from
“0”
to
“1”
when
he/she
presses
the
 buhon
in
response
to
your
call
for
help
 •  When
R
goes
from
“0”
to
“1”,
the
output
Q
 that
controls
the
LED
goes
from
“1”
to
“0”
 thus
the
LED
is
turned
off
 •  Aier
both
buhons
–
S
and
R
–
were
pressed,
 the
iniCal
state
of
the
system
is
restored
 ©
2009
A.
Ganago
 SR
Latch
 22
 ApplicaCon
of
SR
Latch
(2):
 Intruder
Alarm
System

 Circuit
 Security
 personnel
 turns
off
 the
alarm
 ©
2009
A.
Ganago
 PhotosensiCve
Circuit
(example)
 LED
 R2 R1 VOUT Alarm
 VS PD
detects
the
 IR
light
beam

 PD
 PhotosensiCve
Circuit
 detects
an
interrupCon
of
 the
security
light
beam
 SR
Latch
 23
 VOUT LED
emits

 Time infra‐red
(IR)
 light
beam


 InterrupCon
of
light
beam
 produces
a
posiCve
pulse
 ©
2009
A.
Ganago
 SR
Latch
 24
 SR
Latch

 4
 EECS
314
Lecture
notes

 ©
2009
A.
Ganago
 OperaCon
of
the
circuit
(1)
 LED
 VS R1 R2 OperaCon
of
the
circuit
(2)
 LED
 VS R1 R2 Alarm
 Alarm
 PD
 PD
 If
the
light
beam
from
LED
reaches
PD,
 S
is
low,
thus
Q
is
low;
the
Alarm
is
off
 ©
2009
A.
Ganago
 SR
Latch
 25
 Even
a
brief
interrupCon
of
the
light
beam
 drives
Q
high,
thus
turns
on
the
Alarm

 ©
2009
A.
Ganago
 SR
Latch
 26
 OperaCon
of
the
circuit
(3)
 LED
 VS R1 R2 OperaCon
of
the
circuit
(4)
 Alarm
 Alarm
 Circuit
 PD
 Aier
the
light
beam
was
interrupted,
 input
S
returns
to
low,
but
Q
remains
 high
thus
the
Alarm
is
sCll
on
 ©
2009
A.
Ganago
 SR
Latch
 27
 Aier
the
intruder
has
been
stopped,
 security
personnel
turns
off
the
alarm
 by
pressing
the
R
buhon
 ©
2009
A.
Ganago
 SR
Latch
 28
 Other
circuit
soluCon
are
possible
 •  As
an
exercise
(or
exam
problem),
consider
a
 light‐sensiCve
circuit
based
on
a
photoresistor
 (PR)
and
a
Wheatstone
bridge
with
a
 comparator
 •  Recall
that
PR
resistance
increases
when
the
 light
beam
is
interrupted
 •  Assume
that
the
comparator
output
is connected
to
the
S
input
of
SR
latch
 ©
2009
A.
Ganago
 SR
Latch
 29
 Prac5ce
for
the
final
exam
 RSET RA Comp. V2 RPR R2 V1 Is
the
PR
connected
correctly
in
 order
to
build
an
intruder
detector?
 ©
2009
A.
Ganago
 SR
Latch
 30
 SR
Latch

 5
 ...
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This note was uploaded on 12/06/2010 for the course EECS 314 taught by Professor Ganago during the Spring '07 term at University of Michigan.

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