SR Latch - EECS314Lecturenotes 2009A.Ganago...

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EECS 314 Lecture notes © 2009 A. Ganago SR Latch 1 Set‐Reset (SR) Latch: CombinaCon of logic gates that acts as a 1‐bit memory cell Here we consider normal operaCon of the latch: The two inputs – Set (S) and Reset (R) – never equal “1” at the same Cme © 2009 A. Ganago 1 SR Latch A Logic Gate does not have memory The Logic Gate output is enCrely determined by its inputs at the parCcular moment of Cme (for example, described in a Truth table) When we look up the Truth table, we do not worry about what happened with the system in the past Events of the past do not influence how the Logic Gate responds to the present inputs. © 2009 A. Ganago SR Latch 2 CombinaCons of Logic Gates can have memory However, a combinaCon of two NOR gates can act as a 1‐bit storage device It is the simplest “Latch”, called Set‐Reset (SR) Other latches can be built with NAND gates More advanced latches exist, for example, those whose operaCon is linked to parCcular Cming sequences dictated by the clock pulses. © 2009 A. Ganago SR Latch 3 NOR Gate and its Truth table Input Input Output A B C 0 0 1 1 0 0 0 1 0 1 1 0 © 2009 A. Ganago SR Latch 4 NOR A B C SR Latch: Block Diagram © 2009 A. Ganago SR Latch 5 Set Reset Q Q Set (S ) and Reset (R ) are the inputs. Q and Q‐bar are the outputs. SR Latch: AlternaCve Block Diagram © 2009 A. Ganago SR Latch 6 Set Reset Q Q Set (S ) and Reset (R ) are the inputs. Q and Q‐bar are the outputs.
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EECS 314 Lecture notes © 2009 A. Ganago SR Latch 2 SR Latch: OperaCon In the SR latch, the output of one NOR gate is fed into the other NOR gate as input thus it becomes very important to follow the cause‐ and‐effect relaConships of signals In many real circuits, the signals are fed into gates of MOSFETs that act as capacitors that need Cme to go from LOW to HIGH voltage Thus we show delays on Cming diagrams Let us begin with a single NOR gate © 2009 A. Ganago SR Latch 7 Cause‐and‐Effect in NOR gate (1) © 2009 A. Ganago SR Latch 8 Time ”1” “0” ”1” “0” ”1” “0” A A B B C C Example 1 * Cause‐and‐Effect in NOR gate (2)
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