EE 330 Homework 1 Fall 200 9 Due Friday Aug 2 8 Problem 1 Assume a simple circuit requires 500 MOS transistors on a die and that all transistors are minimum sized. If the transistors are fabricated in a 32nm CMOS process and the spacing overhead for the transistors is a factor of 10, determine the number of die that can be fabricated on an 12” silicon wafer. Neglect the area required for the bonding pads of the circuit. Problem 2 If the cost of a 12 inch wafer is $6000, what is the cost/die for the circuit in Problem 1. Problem 3 For small circuits, the area required for bonding pads often dominates the area required for a circuit whereas for large circuits, the bonding pad area is a minor contributor to the overall die area. If bonding pads are square and of area 80 μ x 80 μ and the spacing between bonding pads and between any circuit components is 40 μ , determine the number of die for the 500 transistor circuit of Problem 1 if the circuit requires 8 bonding pads. What is the cost/die if the bonding pads are included?
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