exam2-f10 - Full Name CSCI 2400 Fall 2010 Second Midterm...

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Full Name: CSCI 2400, Fall 2010 Second Midterm Exam SOLUTIONS Instructions: Make sure that your exam is not missing any sheets, then write your full name on the front. Put your name or student ID on each page. Write your answers in the space provided below the problem. If you make a mess, clearly indicate your final answer. This exam is OPEN BOOK and you can use a single page of notes. You can not use a computer or calculator. Good luck! Problem Page Possible Score 1 1 20 2 2 20 3 4 20 4 6 20 5 8 20 Total 100
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CSCI-2400-Fall 2010 -1- December 2, 2010 1. [ 20 Points ] The following problem concerns basic cache lookups and layouts. In all the problems, the memory is byte adressable, and memory accesses are all to bytes (not words). (a) [ 6 Points ] If the cache is 8-way set associative, with an 16-byte block size and 256 total bytes, label the parts of the address uses as the block offset (BO) within the line, the cache set index (CI) and the cache tag (CT). CT CT CT CT CT CT CT CI BO B0 BO BO Answer: The number of sets is equal to 256/(8*16) = 2, so the number of bits for the CI is 1. BO=bits 0-3 (4 bits), CI=4 (1 bits), CT=5-11 (7 bits) (b) [ 3 Points ] Assume the cache size in the first problem was doubled and that the block size was also doubled from 16 to 32 bytes. Would the associativity or number of sets need to change? Answer: The associativity and the number of sets wouldn’t need to change. (256*2)/(2*8*16) = 256/(8*16) * (2/2) = 256/(8*16) = 2. (c) [ 3 Points ] Assume the cache size in the first problem was doubled and that the block size remained the same. What changes would you need to make to the either the associativity or the number of sets? Answer: You’d need to double one or the other (i.e. go from 8-way to 16-way or two sets to 4 sets). (d) [ 5 Points ] A computer system has a 2-level cache. The miss rate of the Level-1 cache is M 1 and the access time when you hit is T 1 . The miss rate of the Level-2 cache is M 2 and the access time to bring a reference from L-2 to L-1 is T 2 . The access time of main memory is T 3 . A reference that misses in one cache level spends access time for that level and the effective access time to bring the item into its cache ( i.e. a reference that misses in the L1 and L2 cache would take T 1 + T 2 + T 3 cycles). Give an expression for the average access time in terms of miss rates and the access times. Answer: (1 - M 1 ) * T 1 + M 1 * ( T 2 + M 2 * T 3 ) = (1 - M 1 ) * T 1 + M 1 * T 2 + M 1 * M 2 * T 3 (e) [ 3 Points ] Assume an L1 cache with a 5% miss rate and a 2-cycle hit time, coupled with an L2 cache with a 5% miss rate and a 12-cycle access time with a main memory access time of 100 cycles. What’s the average memory access time? Answer: 2.75 cycles If you just plugged into the equation, you’ll get credit, but the problem was structured to make the math easy ( . 95 * 2 = 1 . 9 , 0 . 05 * 12 = . 5 + . 1 = . 6 , . 05 * . 05 * 100 = . 0025 * 100 = . 25 so total is 2 . 75 ).
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