solution-exam2-f09 - Full Name CSCI 2400 Fall 2009 Second...

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Full Name: CSCI 2400, Fall 2009 Second Midterm Exam SOLUTIONS Instructions: Make sure that your exam is not missing any sheets, then write your full name on the front. Put your name or student ID on each page. Write your answers in the space provided below the problem. If you make a mess, clearly indicate your final answer. This exam is OPEN BOOK and you can use a single page of notes. You can not use a computer or calculator. Good luck! Problem Page Possible Score 1 1 20 2 2 20 3 3 20 4 6 20 5 8 20 Total 100
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CSCI-2400-Fall 2009 -1- November 18, 2009 1. [ 20 Points ] The following problem concerns basic cache lookups and layouts. In all the problems, the memory is byte adressable, and memory accesses are all to bytes (not words). (a) [ 5 Points ] If the cache is 4-way set associative, with an 8-byte block size and 1024 total bytes, label the parts of the address uses as the block offset (BO) within the line, the cache set index (CI) and the cache tag (CT). CT CT CT CT CT CI CI CI CI B0 BO BO Answer: BO=bits 0-2 (3 bits), CI=3-7 (4 bits), CT=8-11 (4 bits) (b) [ 5 Points ] If the cache is 2-way set associative, with a 4-byte block size and 256 total bytes, label the parts of the address uses as the block offset (BO) within the line, the cache set index (CI) and the cache tag (CT). CT CT CT CT CT CI CT CI CI CI BO BO Answer: BO=0-1 (2 bits), CI=2-6 (5 bits), CT=7-11 (5 bits) (c) [ 5 Points ] Assume you’re designing a cache for a computer that will mainly be used to run workloads with strong spatial locality. For a cache of a given size, what attribute of the cache is likely to be the most important? Answer: The block size - you’d like it to be as large as possible. (d) Assume that it takes 200 CPU cycles to access main memory, and two cycles to access data from the cache. i. [ 2 Points ] What is average number of cycles per memory reference when using a cache that has a 95% hit rate. Answer: 0 . 95 * 2 + 0 . 05 * 200 = 11 . 9 cycles, or 12 CPU cycles. ii. [ 3 Points ] You’re able to either a) decrease the cache access time to 1 cycle; or, b) double the size, increasing the hit rate to 99%; or, c) decrease the memory access time to 100 cycles. Which alternative is better? Answer: One cycle access gives 0 . 95 * 1+0 . 05 * 200 = 10 . 95 cycle access. Hit rate of 99% gives 0 . 99 * 2+0 . 01 * 200 = 3 . 98 cycles, and memory access of 100 cycles is 0 . 95 * 2 + 0 . 05 * 100 = 6 . 9 cycles. Improving the hit rate is the best option.
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  • Fall '08
  • GRUNDWALD
  • CPU cache, Cache algorithms, BO BO

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