03 - Chapter 3 Fundamental Principles of Packet Switch...

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Chapter 3 Fundamental Principles of Packet Switch Design
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Fig. 3.1. Packet arrivals in a 4×4 packet switch 3 1 1 4 2 4 1 1 4 2 4×4 Switch 1 2 3 4 Output destinations are random Idle slots (no active packets) Arrival boundaries may be unaligned
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Fig. 3.2. Input packet processor Disassembler Delay Assembler Header Processor Info Header Memory Input VCI Output Address Output VCI 1 5 2 2 12 5 . . . . . . To Switch Input ( Input VCI ) ( Output VCI )
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VCI of a virtual channel may change from link to link 2 2 3 2 2 2 — Simplify VCI assignment algorithm — Reduce blocking due to shortage of valid VCI
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Fig. 3.3. (a) Speeding up switch operation by N times 1 1 1 2 4 × 4 1 2 3 4 Packets may be switched one by one to outputs if speedup is N times, not viable for large N Contention Problem:
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Loss System : — No input or internal buffers. — A contention resolution mechanism is needed. — Packets which have lost contention will be dropped. — Output buffers are needed if group size is greater than 1. — Loss probability can be made arbitrarily small by adjusting the group size.
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Fig. 3.3. (b) Dropping packets that cannot be switched One of these packets must be dropped if group size = 2 1 1 1 2 4 x 4 1 2 3 4 Loss System:
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Waiting System : — Input or internal buffers are available. — The contention resolution mechanism is still needed. — Packets which have lost contention will be buffered at input or internal buffers. — Output buffers are needed if group size is greater than 1 — Throughput can be made arbitrarily close to 100% by increasing the group size.
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Fig. 3.3. (c) Queueing packets that cannot be switched Two of these packets must be buffered if group size = 1 1 1 1 2 4 x 4 1 2 3 4 Waiting System:
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Interconnection Networks : — Originally intended for multiprocessor computer interconnection — distributed, self-routing algorithms — regular topological interconnection pattern Rearrangeable nonblocking in circuit switching is the same as internally nonblocking in packet switching Speed is the practical difference !
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Fig. 3.4. (a) shuffle-exchange (omega) network; (b) reverse shuffle- exchange network; (c) banyan network ; (d) baseline network Networks (a) and (c) are isomorphic: one can be obtained from the other by interchanging the shaded elements * Unique path from any input to any output * log 2 N stages, each with N/2 2 × 2 switch element. * Not internally nonblocking (a) (b) (c) (d)
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Why does it work? 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 101 100 101 101 100 100 000 001 010 011 100 101 110 111 Destination addresses are in binary form. The log 2 N-bit address is used as the routing bits for the packet: bit i is used in stage i Fig. 3.5. Routing in the banyan network
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Fig. 3.6. Internal and external conflicts when routing packets in a banyan network 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 000 111 000 001 010 011 100 101 110 111 000 100 000 000 One packet must be dropped Internal Conflict 0 1 0 1 0 0 1 External (Output) Conflict
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Loss probability in a Banyan Network : 4 4 4 4 : ion Approximat 4 ) 2 1 ( 1 load offered the , 1} m stage at input an at packet a { Pr 0 0 0 0 0 0 2 1 2 2 1 0 0 + = - = + = - = + = - = - - = = + 5 = + + ρ n n P P m P P dm dP dm dP P P P P P P P P n loss m m m m m m m m m m m m + 1 P m P
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This note was uploaded on 12/08/2010 for the course IEG IEG4020 taught by Professor Fengshen during the Spring '10 term at CUHK.

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03 - Chapter 3 Fundamental Principles of Packet Switch...

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