04 - Chapter 4 Switch Performance Analysis and Design...

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1 Chapter 4 Switch Performance Analysis and Design Improvements
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2 N N p ) 1 ( 1 0 ρ - = - 0 1 ) 1 ( 1 0 ρ ρ - - - - = e N p N for large N For ρ 0 =1, p = 0.632 1 2 3 2 Pr[ carry a packet ] = ρ 0 p = Pr[ carry a packet ] Internally Nonblocking Switch: Loss System
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3 1 2 3 4 1 1 4 3 Outputs Internally Nonblocking Switch Losing packet Winning packet Input Queues Cannot access output 2 because it is blocked by the first packet 3 2 Fig. 3.29. Illustration of head-of-line (HOL) blocking.
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4 1 2 3 4 Outputs Internally Nonblocking Switch (input, output) Fictitious Output Queues formed by HOL packets (1,2) (1,1) (2,3) (2,1) (3,2) (3,2) (4,4) (4,1) (1,2) (3,2) (2,3) (4,4) Output 4 Output 3 Output 2 Output 1 Fig. 4.1. An input-buffered switch with the fictitious queues used for analysis.
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5 Saturation Throughout of Input-Buffered Switch Consider a fictitious queue i = # packets at start of time slot m . = # packets arriving at start of time slot m . i m C i m A i m i m i m A C C + - = ) 1 , 0 max( 1 Number of packets remaining at end of time slot -1 i m B m - =
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6 i 1 i 2 2 i 1 i i i 2 3 i i i Time slot m -1 Fictitious queue i 1 2 i N 3 1 = - i m C 2 i m -1 B = departure i 2 i 1 i i 2 3 i i Time slot m Fictitious queue i 1 2 i N 2 i m -1 B = arrival i i i 4 = i m C 2 = i m A
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7 Saturation Throughout of Input-Buffered Switch Assumption: each time a HOL packet is cleared, there is a next-in-line packet, which is equally likely to be destined for any of the N outputs. is Poisson and independent of as N (see Text for details) i m A Pr[ ] , ! where is the ave. number of cleared HOL packets per time slot k i m A k e k N ρ ρ ρ - = ρ ) 1 ( 0 ] Pr[ ) ( - = = = = z k k e z k A z A
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8 ]... 2 Pr[ ] 1 Pr[ ] 0 Pr[ = + = + = = C z C C ] Pr[ ) ( 0 k B z z B k k = = = ... ] 1 Pr[ ] 0 Pr[ + = + = = B z B ) ( ] 0 Pr[ ) 1 ( 1 1 z C z C z - - + = - = ρ - 1 1 1 ( ) ( ) ( ) [(1 )(1 ) ( )] ( ) C z B z A z z z C z A z ρ - - = = - - + ) 1 )( ( ) 1 ( )) ( )( ( ρ - - = - z A z z A z z C ) 1 )( 1 ( ' 2 ) 1 ( " )) 1 ( ' 1 )( 1 ( ' 2 ρ - = - - A A A C 2 ρ ρ ρ 1 when saturated 586 . 0 2 2 0 2 4 2 = - = = + - ρ ρ ρ
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9 Meaning of Saturation Throughput 1. Let be the saturation throughput of the input- buffered switch with FIFO discipline. 2. When the offered load , the throughput , the system is stable. 3. When the offered load , the throughput , the system is saturated. In this case, with probability 1 the buffer will overflow. 586 . 0 * = ρ * 0 ρ ρ < 0 ρ ρ = * 0 ρ ρ * ρ ρ = 0 ρ ρ Input buffer
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10 How about small N? What if FIFO constraint removed ? - Look-ahead scheme : look at first w packets at each queue. - Cost ε = overhead of one round of contention * ( ) 1 w w ρ ε + N ρ * 2 0.75 3 0.68 4 0.66 5 0.64 w ρ * ( w ) 1 0.59 2 0.70 3 0.76 4 0.80 1
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11 Output 1 Fictitious Queues Output 2 Output N Input Queue Time spent in HOL are independent for successive packets when N is large Service times at different fictitious queues are independent 2 N HOL 1/N 1/N 1/N Fig. 4.2. Queuing scenario for the delay analysis of the input-buffered switch.
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12 X 0 X 3 X 2 X 1 X 0 Busy period Idle period Busy period Y t U(t) Arrivals here are considered as arrivals in intervals i-2 Arrivals here are considered as arrivals in intervals i-1 X i-1 X i Fig. 4.3. The busy periods and interpretations for delay analysis of an input queue.
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13 m i =2 prior arrivals Arrival of the packet of focus. One
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