# 05 - Chapter 5 Advanced Switch Design Principles 1 Packet...

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1 Chapter 5 Advanced Switch Design Principles

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2 mux mux 1st Banyan Network 2nd Banyan Network Kth Banyan Network Packet filter for marked packets Packet filter for unmarked packets Output 1 Output N Fig. 5.1. The tandem-banyan network.
3 (k+1) th Banyan Network (k+2) th Banyan Network MUX ρ k k+1 c k+1 k = k+1 + c k+1 Fig. 5.2. Relationship between the offered load k , carried load c k+1 , and rejected load k+1 of the (k+1)th Banyan network in a tandem- Banyan network.

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4 ρ k+1 = ρ k - ( ρ k+1 ) c ρ k - 4 ρ k /(n ρ k +4) = n ρ k 2 /(n ρ k +4) Let L k = ρ k / ρ o be the probability that a packet still fails to reach its destination after traveling through k Banyan networks. Note that L 0 = 1, L K =P loss . L k+1 = ρ k+1 / ρ o = n ρ k 2 /[ ρ o (n ρ k +4)] = n ρ o L k 2 /(n ρ o L k +4) L k+1 - L k dL k /dk = -4L k /(n ρ o L k +4) k = (n ρ o /4)(1- L k ) - ln L k Thus K = ( ρ o ·log 2 N / 4)(1- P loss ) - ln P loss Complexity: O( log 2 N ) Analysis of Tandem-Banyan Networks
5 2n-1 2n-2 n+j-1 n+1 n j 1 0 Fig. 5.3. The state-transition diagram of tandem-banyan network.

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6 n n-1 j 1 0 Fig. 5.4. The state-transition diagram of shuffle-exchange network.
7 Fig. 5.5. Algebraic operations of shuffle and exchange. 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 Perfect Shuffle Perfect Shuffle + Exchange Packet on link x 3 x 2 x 1 x 2 x 1 x 3 Packet on link x 3 x 2 x 1 x 2 x 1 d 3 d 3 = routing bit

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8 00 01 10 11 00 01 10 11 00 01 10 11 101 101 101 101 i th bit of destination address used for routing at i th stage. Sliding window routing: packet with source-destination label s n …s n-i …s 1 d n …d n-i+1 …d 1 occupies link s n-i …s 1 d n …d n-i+1 …d 1 after stage i . Fig. 5.6. Routing in shuffle-exchange network.
9 00 01 10 11 00 01 10 00 01 10 11 00 01 10 11 00 01 10 11 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 101 101 101 101 100 100 100 100 100 100 101 Packet A Packet B 100 Bypass B deflected A reaches destination 100 100 100 100 100 Routing bit used by B at each stage Fig. 5.7. A shuffle-exchange network with n = 3 and L = 5.

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10 00 01 10 11 0 1 0 1 0 1 0 1 Fig. 5.8. A 4-node feedback shuffle network.
11 Node and Link Labels in Feedback Network x n … x 1 0 x n … x 1 1 x n … x 1 x n-1 … x 1 1 x n-1 …x 1 1x n S = s n … s 1 --> s n-1 … s 1 d n ---> s n-2 …s 1 d n d n-1 --> d n … d 1 = D

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12 Design issues in feedforward network L , P loss Design issues in feedback network Throughput
13 Output Buffer Input Buffer 2x2 Deflection Switch Mechanism for removal and injection of packets One-packet Buffer Fig. 5.9. A node in the feedback shuffle network.

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14 Analysis T i = E [ # additional steps | packet in state i ] T i = 1 + pT i-1 +qT ; 1 i n T 0 = 0 Solving linear difference equations. T n = (1-p n )/(p n q) ρ = link loading success prob. failure prob.
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## 05 - Chapter 5 Advanced Switch Design Principles 1 Packet...

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