07 - Chapter 7 Basic Concepts of Broadband Communication...

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1 Chapter 7 Basic Concepts of Broadband Communication Networks
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2 Outline Synchronous Transfer Mode (STM) Historical Perspective of ATM Delays in ATM network Cell Networking, Virtual Channels, Virtual Paths. ATM Layer, Adaptation Layer and Service Class Transmission Interface ATM Cell Format
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3 Transport Rate hierarchy 64 kbps (basic rate for voice communication) DS-1 rate (1.5 Mbps, 24 basic data rate, the carrier system is called the T-1 link) DS-3 rate (45 Mbps, 28 DS-1 signals) The STM switches are designed to switch at one of the basic rates. What is the difference between switching at DS-1 rate and at DS-3 rate?
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4 DS-1 DS-1 DS-1 DS-1 DS-1 DS-1 Switching at DS-1 rate TDM Channels in DS-1, if any, are not demultiplexed.
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5 DS-0 Channels must be taken apart. DS-1 DS-1 Switching at DS-0 rate
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6 DS-0 Switch TSI TSI TSI 1 2 3 TSI TSI TSI DS-1 line (1,3) (3,2) Time slot DS-1 frame Frame boundary ( i , j ) : The time slot is destined for time slot j of output i . Fig. 7.1. A T-S-T DS-0 switch with DS-1 line interface.
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7 Only the basic rate is allowed Limitation #1
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8 Multirate channels n × basic rate, n = integer < # slots in a frame Achieved by Inverse Multiplexing Multirate Circuit Switching (i) Resequencing. At backend of a basic rate switch (ii) Use a multirate circuit switch
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9 INV MUX Network 256 kbps INV DEMUX 256 kbps Network not aware inv. mux is being used. 4 DS-0 channels Inverse Multiplexing (at network level)
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10 Network Multirate Switch n x 60 kbps -switching 256 kbps 256 kbps N × basic rate Multirate Switching
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11 (a) Using basic rate switch to switch multirate connections T-S-T T-S-T T-S-T T-S-T T-S-T T-S-T T-S-T T-S-T T-S-T An interconnection of T-S-T switch modules Resequencing necessary Frame alignment delay Three slots of the same connection in a frame
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12 T-S-T T-S-T T-S-T T-S-T T-S-T T-S-T T-S-T T-S-T T-S-T Switch the time slots of the same connection as a bundle along the same path (b) Using multirate switch to switch multirate connections Resequencing unnecessary
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13 Limitation #2: Need to recognize logical relationship among time slots. Limitation #3: Only rates that are multiples of basic rate allowed. Limitation (continue)
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14 New Problem : Contention Resolution – New Advantage : Statistical MUX Remove the Frame Structure!
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15 Packet switching as a way to build a “programmable” network Header --- Instructions in computers SS7 network
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16 Processing delay; switching delay; queuing delay (at input, output, or inside the switch fabric, depending on the architecture); transmission delay at each switch node Network Source Destination Adaptation delay ( processing and waiting ); queuing delay after adaptation Propagation delay at each link in the network Adaptation delay (processing and delay compensation using buffer) Fig. 7.3. Delay components of cells from source to destination.
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17 Adaptation Delay at the source * Segmentation * Assembly Stream message Assembler 53-byte (48 bytes pay load) 1 byte e.g. voice: 64 kbps, one cell 400 bits, cell assembly time 400/64
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  • Spring '10
  • FENGShen
  • Asynchronous Transfer Mode, VC switch VPI, Switch VC Switch, VC logical network, VCI VPI VCI

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