Lec_35_ESC102N_MUX

Lec_35_ESC102N_MUX - 4­to­1 Mux I0 I1 I2 I3 4 − to −...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 4­to­1 Mux I0 I1 I2 I3 4 − to − 1 MUX S1 S 0 S1 S 0 Z 0 0 I0 0 1 I1 1 0 I2 Truth table 1 1 I 3 Lecture 35 1 Z 10/28/2010 8­to­1 Mux I0 I1 I2 I3 I4 I5 I6 I7 Z 8 − to − 1 MUX E 1 0 0 0 0 0 0 0 0 E S 2S1 S 0 E = Active low enable 10/28/2010 Lecture 35 S2 X 0 0 0 0 1 1 1 1 S1 X 0 0 1 1 0 0 1 1 S0 Z X0 0 I0 1 I1 0 I2 1 I3 0 I4 1 I5 0 I6 1 I7 2 16­to­1 MUX using 8­to­1 MUX I8 I9 I10 I11 I12 I13 I14 I15 I0 I1 I2 ZI 3 I4 I5 I6 I7 8 − to − 1 MUX S0 S1 S2 S3 8 − to − 1 MUX E S 2S1 S 0 10/28/2010 E S 2S1 S 0 Lecture 35 3 MUX for function generation VCC I 0 I1 I 2 I 3 I 4 I 5 I 6 I 7 A B C 10/28/2010 E S2 S1 8 − to − 1 MUX I0 Lecture 35 S0 Z 4 Function Generator Truth Table A Z = ABC + ABC + ABC 0 0 0 0 1 1 1 1 10/28/2010 Lecture 35 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Z 0 1 1 0 0 0 0 1 5 Implement HA using two 4­to­1 Mux I 0 I1 I 2 I 3 B A S1 S0 4 − to − 1 MUX Z =S VCC I 0 I1 I 2 I 3 S1 S0 B AS C 0000 0110 1010 1101 4 − to − 1 MUX Z =C 10/28/2010 Lecture 35 6 Sequential circuits Sequential circuits are the circuits whose output depends not only on input but also on previous history. Im portnat example is Flip Flop made of log ic gates. These circuits Q have memory. FF Input Q Set Re set input input 10/28/2010 Lecture 35 7 S R Latch NAND Latch : Made of NAND Gates Q S R Q S 0 0 1 1 R Qn+1 0 invalid 1 1 0 0 Qn 1 8 10/28/2010 Lecture 35 S R Latch NAND S R Latch : Why S = 0, R = 0 is invalid Made of NAND Gates Q 1 〈 0 1〉 01 S 01 1 〈1 0 〉 R Q 10/28/2010 Lecture 35 9 ...
View Full Document

Ask a homework question - tutors are online