Ch3_Logic_Minimization

Ch3_Logic_Minimization - ECE 223 Digital Circuits and...

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1 Logic Minimization ECE 223 Digital Circuits and Systems
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2 Karnaugh Maps - Introduction 2-Level Logic implementation using SOP or POS is not the most economical in terms of #gates & #inputs A Karnaugh map is a graphical representation of a truth table The map contains one cell for each possible minterm Adjacent cells differ in only one literal; i.e. x (or x’) Function is plotted by placing 1 in cells corresponding to minterms Put 0 in rest of the cells
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3 K Map with 2 Variables m0 m1 1 0 m3 m2 0 1 y x m3 1 1 1 0 0 x m2 0 1 0 y m1 m0 F F =f(x,y) Example, F1 = x’y 1 0 0 1 y x
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