Ch5_Synchronous_Logic

Ch5_Synchronous_Logic - ECE 223 Digital Circuits and...

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1 Synchronous Logic ECE 223 Digital Circuits and Systems
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2 Sequential Circuits ± Combinational circuits ² Output = f (present inputs) ± Sequential circuits ² Output = f (present inputs and past inputs) ² Circuit remembers past history ² Must contain memory inputs k n outputs present state next state combinational circuit memory m m state
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3 Synchronous Sequential Circuits ± A synchronizing, periodic signal, Clock, facilitates the transition from present state to next state ± Memory is provided by flip-flops
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4 SR (Set Reset) Latches ± NOR Latch ± SR = 11 is avoided ± Outputs are not complementary ± Input transition from 11 Æ 00 may cause circuit to: (i) fall into either state, or become meta-stable
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5 SR (Set Reset) Latches ± NAND Latch ± SR = 00 is avoided ± Outputs are not complementary ± Input transition from 00 Æ 11 may cause circuit to: (i) fall into either state, or become meta-stable
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6 SR Latch with control Input ± C = 0 ± Latch retains its state ± C = 1 ± Allows propagation of SR inputs
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7 Data (D) Latch ± Data latch eliminate, the need for complementary inputs ± Outputs are also complementary
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8 Flip-flop ± Latch Is level sensitive to the control signal ² Multiple data transition may cause problem while C =1 ± Flip-flop is edge triggered ² Flip-flop samples the data on Clock transition
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9 Edge Triggered Flip-flop ± Efficient implementation ² Multiple data transitions do not affect the output
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10 J-K Flip-flop ± Versatile flip-flop ² Can be Set, Reset, or Complement (toggle) its output
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Ch5_Synchronous_Logic - ECE 223 Digital Circuits and...

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