arm_demo - ARM Movement Instructions MOVS Rd updates...

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arm_demo 1 ARM Movement Instructions • MOV S Rd, <op2> ; updates N, Z, C Rd = <op2> (copy of <op2> MVN Rd, <op2> ; Rd = 0xF..F EOR <op2> (one’s complement of <op2>) arm_demo 2 OP2 Selection for binary operations • R m – register m is the operand #n – n is the immediate operand • R m shift immediate • R m shift R s arm_demo 3 ALU Arithmetic Instructions ADDS Rd, Rn, <op2> ; updates N, Z, V, C Rd = Rn + <op2> SUBS Rd, Rn, <op2> Rd = Rn - <op2> CMP Rd, <op2> Flags <= Rd - <op2> (difference lost)
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arm_demo 4 ALU Logical Examples TST Rd, <op2> Flags <= Rd AND <op2> TEQ Rd, <op2> Flags <= Rd EOR <op2> • AND S Rd, Rn, <op2> Rd = Rn AND <op2> update N, Z, C arm_demo 5 ALU Logical Examples EOR Rd, Rn, <op2> Rd = Rn EOR <op2> ORR Rd, Rn, <op2> Rd = Rn OR <op2> BIC Rd, Rn, <op2> ;BIt Clear Rd = Rn AND NOT <op2> arm_demo 6 Conditions (1) (opcode suffix) EQ - Z set (equal) NE - Z clear (not equal) HS / CS - C set (unsigned higher or same) LO / CC - C clear (unsigned lower) MI -N set (negative) PL - N clear (positive or zero) VS - V set (overflow) VC - V clear (no overflow) HI - C set and Z clear (unsigned higher)
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arm_demo 7 Conditions (2) (opcode suffix) LS - C clear or Z (set unsigned lower or same) GE - N set and V set, or N clear and V clear (>or =) LT - N set and V clear, or N clear and V set (>) GT - Z clear, and either N set and V set, or N clear and V set (>) LE - Z set, or N set and V clear,or N clear and V set (<, or =) AL – always (default) NV – reserved (don’t use) arm_demo 8 Typical Conditions EQ: last arithmetic operation yielded 0 result last logical operation yielded 0 result last compare when both operands the same NE: last arithmetic operation yielded non-0 result last logical operation yielded non-0 result last compare when operands differed PL: value of MSB is 0 after last operation (result is positive number arm_demo 9 Branch Instructions B label ( BAL label ) PC <= “address” of label B(cond) label PC <= “address” of label if cond is true, otherwise execute next instruction These are not calls to subroutines!
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arm_demo 10 Branch and Link Instructions BL label ( BLAL label ) PC <= “address” of label, set link register to current PC value BL(cond) label PC <= “address” of label if cond is true, set link register to current PC value, otherwise execute next instruction These are calls to subroutines since we remember where we came from. arm_demo 11 <am1> Typical Modes • [R n ] – pointer/register indirect, memory address is content or register [Rn, off] – above with offset added to register [Rn], #4 – post increment of pointer in register (word: #4, byte: #1) arm_demo 12 Load Instructions LDR Rd, <am1> (also LDRB for bytes) Rd = [address] LDM(cond){IB|IA|DB|DA}, Rd(!), <regs>{^} “block pop”, ! => update Rd, <“regs”> => list of registers ^ => set the S bit
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arm_demo 13 Store Instructions STR Rd, <am1> (also STRB for bytes) [address] = Rd STM(cond){IB|IA|DB|DA}, Rd(!), <regs>{^} “block push”, ! => update Rd,
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