chapter10_ex_sol - 1 Chapter 10 Problem Set Chapter 10...

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1 Chapter 10 Problem Set Chapter 10 SOLUTIONS 1. [C, None, 9.2] For the circuit in Figure 0.1, assume a unit delay through the Register and Logic blocks (i.e., t R = t L = 1). Assume that the registers, which are positive edge-triggered, have a set-up time t S of 1. The delay through the multiplexer t M equals 2 t R . a. Determine the minimum clock period. Disregard clock skew. Solution The circuit and paths of interest has been reproduced for convenience in Figure 0.1 Out of the 4 paths shown in the figure, p1 is the critical one and determines the lower bound on the clock period. Using , we get T min = 1+7+1 = 9 . b. Repeat part a, factoring in a nonzero clock skew: δ = t θ t θ = 1 . Solution With finite clock skew, the time periods for different paths are as follows : T min (p1) = 9 - 1 = 8, T min (p2) = 6, T min (p3) = 7, T min (p4) = 7 - 1 = 6 (Note that the clock skew is 0 for paths p2 and p3). Therefore the minimum clock period is T min = 8 . c. Repeat part a, factoring in a non-zero clock skew: δ = t θ t θ = 4 . Solution As the clock skew increases, the most significant path changes. Repeating the calcula- tions in part (b) we get : T min (p1) = 9 - 4 = 5, T min (p2) = 6, T min (p3) = 7, T min (p4) = 7 - 4 = 3(Note that the clock skew is 0 for paths p2 and p3). Therefore the minimum clock period is T min = 7 . Logic Register p1 p2 p3 p4 t θ t θ Θ Figure 0.1 Sequential circuit. Tt reg t ic log t setup δ ++
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2 Chapter 10 Problem Set d. Derive the maximum positive clock skew that can be tolerated before the circuit fails. Solution The maximum positive clock skew is determined by the inequal- ity . Assuming that the contamination delay is same as the propagation delay, we get. = 1 + 3 + 2 = 6 . Note that p4 determines the maximum tolerable skew (the fastest path will produce the earliest contamination). Paths p3 and p2 do not matter since there is no skew involved. e. Derive the maximum negative clock skew that can be tolerated before the circuit fails. Solution The maximum positive negative skew has no bound since the clock period has no upper bound. 2. This problem examines sources of skew and jitter. a. A balanced clock distribution scheme is shown in Figure 0.2. For each source of variation, identify if it contributes to skew or jitter. Circle your answer in Table 0.1 δ t cd reg , t cd ic log , + δ max Clock Generation Devices Power Supply Noise Interconnect Data Dependent Load Static Temperature Gradient 6 1 2 3 4 5 Figure 0.2 Sources of Skew and Jitter in Clock Distribution. 1) Uncertainty in the clock generation circuit Skew Jitter 2) Process variation in devices Skew Jitter 3) Interconnect variation Skew Jitter 4) Power Supply Noise Skew Jitter 5) Data Dependent Load Capacitance Skew Jitter 6) Static Temperature Gradient Skew Jitter Table 0.1 Sources os Skew and Jitter
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Digital Integrated Circuits - 2nd Ed 3 b. Consider a Gated Clock implementation where the clock to various logical modules can be individually turned off as shown in Figure 0.3. (i.e., Enable 1 ,..., Enable N can take on dif- ferent values on a cycle by cycle basis). Which approach ( A or B ) results in lower jitter at the output of the input clock driver? (hint: consider gate capacitance)
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This note was uploaded on 12/10/2010 for the course DCIS 32 taught by Professor Go during the Spring '10 term at College of E&ME, NUST.

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chapter10_ex_sol - 1 Chapter 10 Problem Set Chapter 10...

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