chapter5_ex_sol - CHAPTER 5 THE CMOS INVERTER...

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180 CHAPTER 5 THE CMOS INVERTER Quantification of integrity, performance, and energy metrics of an inverter Optimization of an inverter design 5.1 Exercises and Design Problems 5.2 The Static CMOS Inverter — An Intuitive Perspective 5.3 Evaluating the Robustness of the CMOS Inverter: The Static Behavior 5.3.1 Switching Threshold 5.3.2 Noise Margins 5.3.3 Robustness Revisited 5.4 Performance of CMOS Inverter: The Dynamic Behavior 5.4.1 Computing the Capacitances 5.4.2 Propagation Delay: First-Order Analysis 5.4.3 Propagation Delay from a Design Perspective 5.5 Power, Energy, and Energy-Delay 5.5.1 Dynamic Power Consumption 5.5.2 Static Consumption 5.5.3 Putting It All Together 5.5.4 Analyzing Power Consumption Using SPICE 5.6 Perspective: Technology Scaling and its Impact on the Inverter Metrics
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Section 5.1 Exercises and Design Problems 181 5.1 Exercises and Design Problems 1. [M, SPICE, 3.3.2] The layout of a static CMOS inverter is given in Figure 5.1. ( λ =0 .125 μm). a. Determine the sizes of the NMOS and PMOS transistors. Solution The sizes are w n =1.0μm, l n =0.25μm, w p =0.5μm, and l p =0.25 μm. b. Plot the VTC (using HSPICE) and derive its parameters ( V OH , V OL , V M , V IH ,and V IL ). Solution The inverter VTC is shown below. For a static CMOS inverter with a supply voltage of 2.5 V, V OH =2.5 V and V OL =0 V. In order to calculate V m , note from the VTC that the value is between 0.8 V and 0.9 V. Therefore, the NMOS is saturated and the PMOS is velocity satu- rated. Let V in =V out =V m and set the currents equal to obtain the following equation: (k n /2)(V GS -V TN ) 2 (1+ λ V DS )=k p V DSAT [(V GS -V TP )-(V DSAT /2)](1+ λ V DS ) Substitute the appropriate values and solve numerically to find V m =0.883 V. Use the VTC data to solve for V IL and V IH numerically. The result is that V IH =0.97 V and V IL =0.56 V. c. Is the VTC affected when the output of the gates is connected to the inputs of 4 similar gates? Solution No. CMOS gates are a purely capacitive load so the DC circuit characteristics are not affected. 0 0.5 1 1.5 2 2.5 -0.5 0 0.5 1 1.5 2 2.5 3 Input Voltage (V) Output Voltage (V) V IL V IH V M
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182 THE CMOS INVERTER Chapter 5 d. Resize the inverter to achieve a switching threshold of approximately 0.75 V. Do not lay- out the new inverter, use HSPICE for your simulations. How are the noise margins affected by this modification? Solution Changing the NMOS sizing to w n =2 .0μmmovesthesw i tch ingth resho ldto0 .75V . This increases N MH and decreases N ML . 2. Figure 5.2 shows a piecewise linear approximation for the VTC. The transition region is approximated by a straight line with a slope equal to the inverter gain at V M . The intersection of this line with the V OH and the V OL lines defines V IH and V IL . a. The noise margins of a CMOS inverter are highly dependent on the sizing ratio, r = k p / k n , of the NMOS and PMOS transistors. Use HSPICE with V Tn = | V Tp | to determine the value of r that results in equal noise margins? Give a qualitative explanation.
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This note was uploaded on 12/10/2010 for the course DCIS 32 taught by Professor Go during the Spring '10 term at College of E&ME, NUST.

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chapter5_ex_sol - CHAPTER 5 THE CMOS INVERTER...

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