Lecture7 - Lecture 7 Registers Memory Cache CPU Memory MAR...

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Lecture 7 Registers, Memory, Cache Memory bus of modern machines MAR may or may not be there in CPU . Size of the memory impacts the Width of Address bus, Data bus and Control bus. Address and Data bus is sometimes shared. o Write operation will be affected. Requires 2 clock cycles to send information. 1 cycle for address and 1 cycle for the data. Why did the designers of the JVN machine choose 40 bits for word size? Instruction size was chosen to be 20 bits, (8 for opcode and 12 for address) Today, 20 bits are not sufficient to hold (reasonably) large numbers. We need 30-35 bits to do any meaningful calculations. With a 35-bit word, we waste a lot of bits in the program area since one word would hold only one instruction. With 40 bits, two instructions can stored in one word, saving time and space. Memory CPU MAR MDR Address Data Control
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Problems with Accumulator Machine Most instructions involve use of ACC . X = A + B is our example. This is translated as: LOAD A All three instructions ADD B require a memory STORE X access. While executing our program, memory is accessed in almost every instruction. Typically, memory speed is much less than that of CPU ( ALU + control). Even if our CPU is fast, performance depends on speed of memory. Memory & CPU chips are made using different technology. o In early machines magnetic main memory was used (very slow). o These days we use DRAM (Dynamic Random Access Memory) & SDRAM (Synchronous Dynamic Random Access Memory) chips. o DRAM chips are slower than CPU chips. So we still have the problem. Issue : CPU and memory have speed mismatch. Two Solutions : 1 . Registers and 2 . Cache Memory Use of registers: What if we provide some extra memory locations inside CPU , with same speed?
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Lecture7 - Lecture 7 Registers Memory Cache CPU Memory MAR...

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