FPGA - 1737 Book Page 1 Wednesday, January 22, 2003 8:19 AM...

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0-8493-1737-1/03/$0.00+$1.50 © 2003 by CRC Press LLC 13- 1 13 Logic Synthesis for Field Programmable Gate Array (FPGA) Technology 13.1 Introduction . ..................................................................... 13- 1 13.2 FPGA Structures. ............................................................... 13- 2 Look-up Table (LUT)-Based CLB • PLA-Based CLB • Multiplexer-Based CLB • Interconnect 13.3 Logic Synthesis . ................................................................. 13- 4 Technology Independent Optimization • Technology Mapping 13.4 Look-up Table (LUT) Synthesis. ...................................... 13- 6 Library-Based Mapping • Direct Approaches 13.5 Chortle . .............................................................................. 13- 7 Tree Mapping Algorithm • Example • Chortle-crf • Chortle-d 13.6 Two-Step Approaches. ..................................................... 13- 12 First Step: Decomposition • Second Step: Node Elimination • MIS-pga 2: A Framework for TLU-Logic Optimization 13.7 Conclusion. ...................................................................... 13- 16 13.1 Introduction F ield P rogrammable G ate A rrays (FPGAs) enable rapid development and implementation of complex digital circuits. FPGA devices can be reprogrammed and reused, allowing the same hardware to be employed for entirely new designs or for new iterations of the same design. While much of traditional IC logic synthesis methods apply, FPGA circuits have special requirements that affect synthesis. The FPGA device consists of a number of configurable logic blocks (CLBs) interconnected by a routing matrix. Pass transistors are used in the routing matrix to connect segments of metal lines. There are three major types of CLBs: those based on PLAs, those based on multiplexers, and those based on table look- up (TLU) functions. Automated logic synthesis tools are used to optimize the mapping of the Boolean network to the FPGA device. FPGA synthesis is an extension to the general problem of multi-level logic synthesis. FPGA logic synthesis is usually solved in two phases. The technology - independent phase uses a general multi-level logic optimization tool (such as Berkeley’s MIS) to reduce the complexity of the Boolean network. Next, a technology - dependent optimization phase is used to optimize the logic for the particular type of device. In the case of the TLU-based FPGA, each CLB can implement an arbitrary logic function of a limited John W. Lockwood Washington University Copyright © 2003 CRC Press, LLC
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13- 2 Memory, Microprocessor, and ASIC number of variables. FPGA optimization algorithms aim to minimize the number of CLBs used, the logic depth, and the routing density. The Chortle algorithm is a direct method that uses dynamic programming to map the logic into TLU- based CLBs. It converts the Boolean network into a forest of directed acyclic graphs (DAGs); then it evaluates and records the optimal subsolutions to the logic mapping problem as it traverses the DAG. The two - step algorithms operate by first decomposing the nodes, and then performing a node elimination . Later sections of this chapter discuss in detail the Xmap, Hydra , and MIS - pga algorithms. FPGA devices are fabricated using the same sub-micron geometries as other silicon devices. As such, the devices benefit from the rapid advances in device-technology. The overhead of the programming bits, general function generators, and general routing structures, however, reduce the total amount of logic available to the end user.
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This note was uploaded on 12/15/2010 for the course ECE 271 taught by Professor Garrisongreenwood during the Spring '10 term at Pohang University of Science and Technology.

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FPGA - 1737 Book Page 1 Wednesday, January 22, 2003 8:19 AM...

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