Lec-05-Seq - SequentialLogic SequentialCircuits Latches Clockskew Shiftregisters CS 150 Fall 2000 Sequential Logic 1 TimingMethodologies As

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CS 150 - Fall 2000 - Sequential Logic - 1 Sequential Logic Sequential Circuits Simple circuits with feedback Latches Edge-triggered flip-flops Timing Methodologies Cascading flip-flops for proper operation Clock skew Asynchronous Inputs Metastability and synchronization Basic Registers Shift registers
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CS 150 - Fall 2000 - Sequential Logic - 2 C1 C2 C3 comparator value equal multiplexer reset open/closed new equal mux  control clock comb. logic state Sequential Circuits Circuits with Feedback Outputs = f(inputs, past inputs, past outputs) Basis for building "memory" into logic circuits Door combination lock is an example of a sequential circuit State is memory State is an "output" and an "input" to combinational logic Combination storage elements are also memory
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CS 150 - Fall 2000 - Sequential Logic - 3 X1 X2 Xn switching network Z1 Z2 Zn Circuits with Feedback How to control feedback? What stops values from cycling around endlessly
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CS 150 - Fall 2000 - Sequential Logic - 4 "remember" "load" "data" "stored value" "0" "1" "stored value" Simplest Circuits with Feedback Two inverters form a static memory cell Will hold value as long as it has power applied How to get a new value into the memory cell? Selectively break feedback path Load new value into cell
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CS 150 - Fall 2000 - Sequential Logic - 5 R S Q Q' R S Q R' S' Q Q Q' S' R' Memory with Cross-coupled Gates Cross-coupled NOR gates Similar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1) Cross-coupled NAND gates Similar to inverter pair, with capability to force output to 0 (reset=0) or 1 (set=0)
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CS 150 - Fall 2000 - Sequential Logic - 6 Reset Hold Set Set Reset Race R S Q \Q 100 Timing Behavior R S Q Q'
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CS 150 - Fall 2000 - Sequential Logic - 7 S R Q 0 0 hold 0 1 0 1 0 1 1 1 unstable State Behavior of R-S latch Truth table of R-S latch behavior Q Q' 0  1 Q Q' 1  0 Q Q' 0  0 Q Q' 1  1
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Theoretical R-S Latch Behavior Q Q' 1  0 Q Q' 0  0 Q Q' 1  1 SR=00 SR=11 SR=10 SR=01 SR=00 SR=10 SR=11 SR=11 SR=10 SR=01  SR=01 SR=10 SR=11 possible oscillation between states 00 and 11
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Observed R-S Latch Behavior Very difficult to observe R-S latch in the 1-1 state One of R or S usually changes first Ambiguously returns to state 0-1 or 1-0 A so-called "race condition" Or non-deterministic transition SR=00 SR=00 SR=10 SR=00 SR=01 SR=11 SR=11 SR=01 SR=10 SR=11
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CS 150 - Fall 2000 - Sequential Logic - 10 Q(t+ ) R S Q(t) S R Q(t) Q(t+ ) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 X 1 1 1 X hold reset set not allowed characteristic equation Q(t+ ) = S + R’ Q(t) R-S Latch Analysis Break feedback path R S Q Q' 0 0 1 0 X 1 X 1 Q(t) R S
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CS 150 - Fall 2000 - Sequential Logic - 11 enable' S' Q' Q R' R S Gated R-S Latch Control when R and S  inputs matter Otherwise, the slightest  glitch on R or S while enable  is low could cause  change in value stored Set Reset S' R' enable' Q Q' 100
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This note was uploaded on 12/15/2010 for the course ECE 271 taught by Professor Garrisongreenwood during the Spring '10 term at Pohang University of Science and Technology.

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Lec-05-Seq - SequentialLogic SequentialCircuits Latches Clockskew Shiftregisters CS 150 Fall 2000 Sequential Logic 1 TimingMethodologies As

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