Lec-07-SeqEx - S que e ntial Logic Exam s ple FiniteS...

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CS 150 - Fall 2000 - Sequential Logic Examples - 1 Sequential Logic Examples Finite State Machine Concept FSMs are the decision making logic of digital designs Partitioning designs into datapath and control elements When inputs are sampled and outputs asserted Basic Design Approach: 4-step Design Process Implementation Examples and Case Studies Finite-string pattern recognizer Complex counter Traffic light controller Door combination lock

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CS 150 - Fall 2000 - Sequential Logic Examples - 2 General FSM Design Procedure (1) Determine inputs and outputs (2) Determine possible states of machine – State minimization (3) Encode states and outputs into a binary code – State assignment or state encoding – Output encoding – Possibly input encoding (if under our control) (4) Realize logic to implement functions for states and outputs – Combinational logic implementation and optimization – Choices in steps 2 and 3 have large effect on resulting logic
CS 150 - Fall 2000 - Sequential Logic Examples - 3 Finite String Pattern Recognizer (Step 1) One input (X) and one output (Z) Output is asserted whenever the input sequence …010… has been observed, as long as the sequence 100 has never been seen Step 1: Understanding the Problem Statement Sample input/output behavior: X: 0 0 1 0 1 0 1 0 0 1 0 … Z: 0 0 0 1 0 1 0 1 0 0 0 … 1 1 0 1 1 0 1 0 0 1 0 … Z: 0 0 0 0 0 0 0 1 0 0 0 …

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CS 150 - Fall 2000 - Sequential Logic Examples - 4 Finite String Pattern Recognizer (Step 2) Step 2: Draw State Diagram For the strings that must be recognized, i.e., 010 and 100 Moore implementation S1 [0] S2 [0] 0 1 S3 [1] 0 S4 [0] 0 or 1 S5 [0] 0 0 S6 [0] S0 [0] reset
CS 150 - Fall 2000 - Sequential Logic Examples - 5 Finite String Pattern Recognizer (Step 2, cont’d) Exit conditions from state S3: have recognized …010 If next input is 0 then have …0100 = . ..100 (state S6) If next input is 1 then have …0101 = …01 (state S2) 1 ...01 ...010 ...100 S4 [0] S1 [0] S0 [0] S2 [0] 0 1 reset 0 or 1 S3 [1] 0 S5 [0] 0 0 S6 [0] Exit conditions from S1: recognizes strings of form …0 (no 1 seen); loop back to S1 if input is 0 Exit conditions from S4: recognizes strings of form …1 (no 0 seen); loop back to S4 if input is 1 ...1 ...0 1 0

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CS 150 - Fall 2000 - Sequential Logic Examples - 6 Finite String Pattern Recognizer (Step 2, cont’d) S2 and S5 still have incomplete transitions S2 = …01; If next input is 1, then string could be prefix of (01)1(00) S4 handles just this case S5 = …10; If next input is 1, then string could be prefix of (10)1(0) S2 handles just this case Reuse states as much as possible Look for same meaning State minimization leads to smaller number of bits to represent states Once all states have complete set of transitions we have final state diagram 1 ...01 ...010 ...100 S4 [0] S1 [0] S0 [0] S2 [0] 0 1 reset 0 or 1 S3 [1] 0 S5 [0] 0 0 S6 [0] 1 0 ...10 1
CS 150 - Fall 2000 - Sequential Logic Examples - 7 module string (clk, X, rst, Q0, Q1, Q2, Z); input clk, X, rst; output Q0, Q1, Q2, Z; reg state[0:2]; ‘define S0 = [0,0,0]; //reset state ‘define S1 = [0,0,1]; //strings ending in ...0

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Lec-07-SeqEx - S que e ntial Logic Exam s ple FiniteS...

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