Lec-08-CompOrg - Computer Or gani zati on Computer desi gn...

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CS 150 - Fakk 2000 - Computer Organization - 1 Computer Organization Computer design as an application of digital logic design procedures Computer = processing unit + memory system Processing unit = control + datapath Control = finite state machine Inputs = machine instruction, datapath conditions Outputs = register transfer control signals, ALU operation codes Instruction interpretation = instruction fetch, decode, execute Datapath = functional units + registers Functional units = ALU, multipliers, dividers, etc. Registers = program counter, shifters, storage registers
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CS 150 - Fakk 2000 - Computer Organization - 2 central processing  unit (CPU) instruction unit – instruction fetch and  interpretation FSM execution unit – functional units and registers address read/write data Processor Memory System Structure of a Computer Block diagram view data conditions Data Path Control
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CS 150 - Fakk 2000 - Computer Organization - 3 LD asserted during a lo-to-hi clock  transition loads new data into FFs OE asserted causes FF state to be  connected to output pins; otherwise they  are left unconnected (high impedance) OE Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 LD D7 D6 D5 D4 D3 D2 D1 D0 CLK Registers Selectively loaded – EN or LD input Output enable – OE input Multiple registers – group 4 or 8 in parallel
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CS 150 - Fakk 2000 - Computer Organization - 4 Register Transfer Point-to-point connection Dedicated wires Muxes on inputs of each register Common input from multiplexer Load enables for each register Control signals for multiplexer Common bus with output enables Output enables and load enables for each register rt MUX rs MUX rd MUX R4 MUX rs MUX rt rd R4 BUS rs rt rd R4
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CS 150 - Fakk 2000 - Computer Organization - 5 RE RB RA WE WB WA D3 D2 Q3 Q2 Q1 Q0 Register Files Collections of registers in one package Two-dimensional array of FFs Address used as index to a particular word Separate read and write addresses so can do both at same time 4 by 4 register file 16 D-FFs Organized as four words of four bits each Write-enable (load) Read-enable (output enable)
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CS 150 - Fakk 2000 - Computer Organization - 6 RD WR A9 A8 A7 A6 A5 A4 A3 IO3 IO2 IO1 IO0 Memories Larger Collections of Storage Elements Implemented not as FFs but as much more efficient latches High-density memories use 1-5 switches (transitors) per bit Static RAM – 1024 words each 4 bits wide Once written, memory holds forever (not true for denser dynamic RAM) Address lines to select word (10 lines for 1024 words) Read enable Same as output enable Often called chip select Permits connection of many chips into larger array Write enable (same as load enable) Bi-directional data lines output when reading, input when writing
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CS 150 - Fakk 2000 - Computer Organization - 7 Instruction Sequencing Example – an instruction to add the contents of two registers (Rx and Ry) and place result in a third register (Rz)
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Lec-08-CompOrg - Computer Or gani zati on Computer desi gn...

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