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Lec-10-CntrImpl - Overview on jumpcounters...

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CS 150 - Fall 2000 - Controller Implementation - 1 Overview Alternative controller FSM implementation approaches based  on: classical Moore and Mealy machines jump counters microprogramming (ROM) based approaches branch sequencers horizontal microcode vertical microcode
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CS 150 - Fall 2000 - Controller Implementation - 2 Alternative Ways to Implement Processor  FSMs "Random Logic" based on Moore and Mealy Design Classical Finite State Machine Design Divide and Conquer Approach: Time-State Method Partition FSM into multiple communicating FSMs Exploit MSI Components: Jump Counters Counters, Multiplexors, Decoders Microprogramming: ROM-based methods Direct encoding of next states and outputs
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CS 150 - Fall 2000 - Controller Implementation - 3 Random Logic Perhaps poor choice of terms for "classical" FSMs Contrast with structured logic: PAL/PLA, PGA, ROM Could just as easily construct Moore and Mealy machines with  these components
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CS 150 - Fall 2000 - Controller Implementation - 4 Moore Machine State Diagram Note capture of MBR in these states 0 PC Reset Wait/ Wait/ Wait/ Wait/ Wait/ Wait/ =11 =10 =0 =1 BR0 BR1 IF3 OD =00 =01 AD0 ST0 ST1 AD1 Wait/ Wait/ AD2 Wait/ Wait/ LD0 LD1 LD2 Wait/ Wait/ PC MAR, PC + 1 PC MAR Mem, 1 Read/Write, 1 Request, Mem MBR MBR IR IR MAR IR MAR IR PC MAR Mem, 1 Read/Write, 1 Request, Mem MBR MAR Mem, 0 Read/Write, 1 Request, MBR Mem MAR Mem, 1 Read/Write, 1 Request, Mem MBR MBR AC MBR + AC AC IF2 IF1 IF0 RES IR MAR, AC MBR
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CS 150 - Fall 2000 - Controller Implementation - 5 Memory-Register Interface Timing Valid data latched on IF2 to IF3 transition because data must be  valid before Wait can go low CLK WAIT Mem Bus Latch MBR IF1 IF2 IF2 IF2 IF3 Invalid Data Latched Invalid Data Latched Valid Data Latched Data Valid
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CS 150 - Fall 2000 - Controller Implementation - 6 Moore Machine Diagram 16 states, 4 bit state register Next State Logic: 9 Inputs, 4 Outputs Output Logic: 4 Inputs, 18 Outputs These can be implemented via ROM       or PAL/PLA Next State: 512 x 4 bit ROM Output:  16 x 18 bit ROM Next State Logic Clock State Reset Wait IR<15> IR<14> AC<15> Output Logic Read/Write Request 0 PC PC + 1 PC PC ABUS IR ABUS ABUS MAR ABUS PC MAR Memory Address Bus Memory Data Bus MBR MBR Memory Data Bus MBR MBUS MBUS IR MBUS ALU B MBUS AC RBUS AC RBUS MBR ALU ADD
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CS 150 - Fall 2000 - Controller Implementation - 7 Moore Machine State Table Reset Wait IR<15> IR<14> AC<15> Current State Next State Register Transfer Ops 1 X X X X X RES (0000) 0 X X X X RES (0000) IF0 (0001) PC 0 X X X X IF0 (0001) IF1 (0001) PC   MAR, PC + 1   PC 0 0 X X X IF1 (0010) IF1 (0010) 0 1 X X X IF1 (0010) IF2 (0011) 0 1 X X X IF2 (0011) IF2 (0011) MAR   Mem, Read, 0 0 X X X IF2 (0011) IF3 (0100) Request, Mem   MBR 0 0 X X X IF3 (0100)
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