Lec-10-CntrImpl - CS 150 - Fall 2000 - Controller...

Info iconThis preview shows pages 1–8. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: CS 150 - Fall 2000 - Controller Implementation - 1 Overview • Alternative controller FSM implementation approaches based on: – classical Moore and Mealy machines – jump counters – microprogramming (ROM) based approaches – branch sequencers – horizontal microcode – vertical microcode CS 150 - Fall 2000 - Controller Implementation - 2 Alternative Ways to Implement Processor FSMs • "Random Logic" based on Moore and Mealy Design – Classical Finite State Machine Design • Divide and Conquer Approach: Time-State Method – Partition FSM into multiple communicating FSMs • Exploit MSI Components: Jump Counters – Counters, Multiplexors, Decoders • Microprogramming: ROM-based methods – Direct encoding of next states and outputs CS 150 - Fall 2000 - Controller Implementation - 3 Random Logic • Perhaps poor choice of terms for "classical" FSMs • Contrast with structured logic: PAL/PLA, PGA, ROM • Could just as easily construct Moore and Mealy machines with these components CS 150 - Fall 2000 - Controller Implementation - 4 Moore Machine State Diagram Note capture of MBR in these states 0 → PC Reset Wait/ Wait/ Wait/ Wait/ Wait/ Wait/ =11 =10 =0 =1 BR0 BR1 IF3 OD =00 =01 AD0 ST0 ST1 AD1 Wait/ Wait/ AD2 Wait/ Wait/ LD0 LD1 LD2 Wait/ Wait/ PC → MAR, PC + 1 → PC MAR → Mem, 1 → Read/Write, 1 → Request, Mem → MBR MBR → IR IR → MAR IR → MAR IR → PC MAR → Mem, 1 → Read/Write, 1 → Request, Mem → MBR MAR → Mem, 0 → Read/Write, 1 → Request, MBR → Mem MAR → Mem, 1 → Read/Write, 1 → Request, Mem → MBR MBR → AC MBR + AC → AC IF2 IF1 IF0 RES IR → MAR, AC → MBR CS 150 - Fall 2000 - Controller Implementation - 5 Memory-Register Interface Timing Valid data latched on IF2 to IF3 transition because data must be valid before Wait can go low CLK WAIT Mem Bus Latch MBR IF1 IF2 IF2 IF2 IF3 Invalid Data Latched Invalid Data Latched Valid Data Latched Data Valid CS 150 - Fall 2000 - Controller Implementation - 6 Moore Machine Diagram 16 states, 4 bit state register Next State Logic: 9 Inputs, 4 Outputs Output Logic: 4 Inputs, 18 Outputs These can be implemented via ROM or PAL/PLA Next State: 512 x 4 bit ROM Output: 16 x 18 bit ROM Next State Logic Clock State Reset Wait IR<15> IR<14> AC<15> Output Logic Read/Write Request 0 → PC PC + 1 → PC PC → ABUS IR → ABUS ABUS → MAR ABUS → PC MAR → Memory Address Bus Memory Data Bus → MBR MBR → Memory Data Bus MBR → MBUS MBUS → IR MBUS → ALU B MBUS → AC RBUS → AC RBUS → MBR ALU ADD CS 150 - Fall 2000 - Controller Implementation - 7 Moore Machine State Table Reset Wait IR<15> IR<14> AC<15> Current State Next State Register Transfer Ops 1 X X X X X RES (0000) X X X X RES (0000) IF0 (0001) 0 → PC X X X X IF0 (0001) IF1 (0001) PC → MAR, PC + 1 → PC...
View Full Document

This note was uploaded on 12/15/2010 for the course ECE 271 taught by Professor Garrisongreenwood during the Spring '10 term at Pohang University of Science and Technology.

Page1 / 48

Lec-10-CntrImpl - CS 150 - Fall 2000 - Controller...

This preview shows document pages 1 - 8. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online