Lec-12-FPGAsa - ImplementationStrategies ROMbasedDesign

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Xilinx FPGAs - 1 ROM-based Design Example: BCD to Excess 3 Serial Converter BCD Excess 3 Code 0000 0011 0001 0100 0010 0101 0011 0110 0100 0111 0101 1000 0110 1001 0111 1010 1000 1011 1001 1100 Conversion Process Bits are presented in bit serial fashion starting with the least significant bit Single input X, single output Z Implementation Strategies
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Xilinx FPGAs - 2 State Transition Table Derived State Diagram Present State S0 S1 S2 S3 S4 S5 S6 Next State Output X=0 S1 S3 S4 S5 S5 S0 S0 X=1 S2 S4 S4 S5 S6 S0 -- X=0 1 1 0 0 1 0 1 X=1 0 0 1 1 0 1 -- Reset S0 0/1 1/0 S1 0/1 1/0 S2 0/0, 1/1 S3 0/0, 1/1 S4 1/0 0/1 S5 0/0, 1/1 S6 0/1 Implementation Strategies
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Xilinx FPGAs - 3 ROM-based Implementation Truth Table/ROM I/Os Circuit Level Realization 74175 = 4 x positive edge triggered D FFs In ROM-based designs, no need to consider state assignment QA QA QB QB QC QC QD QD CLK CLR 1 converter ROM X Q2 Q1 Q0 Z D2 D1 D0 15 14 10 11 7 6 2 3 D C B A CLK 13 12 1 0 \Reset X 1 0 175 1 Z 9 5 4 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Q2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D2 0 0 1 1 1 0 0 X 0 1 1 1 1 0 X X Z 1 1 0 0 1 0 1 X 0 0 1 1 0 1 X X D1 0 1 0 0 0 0 0 X 1 0 0 0 1 0 X X D0 1 1 0 1 1 0 0 X 0 0 0 1 0 0 X X ROM Address ROM Outputs Implementation Strategies
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Xilinx FPGAs - 4 Timing Behavior for input strings 0 0 0 0 (0) and 1 1 1 0 (7) 0 0 0 0                   1 1 0 0 1 1 1 0                   0 1 0 1 LSB MSB LSB LSB 0 0 0 0 1 1 0 0 1 1 1 0 0 1 0 1 Implementation Strategies
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Xilinx FPGAs - 5 PLA-based Design State Assignment with NOVA S0 = 000 S1 = 001 S2 = 011 S3 = 110 S4 = 100 S5 = 111 S6 = 101 NOVA derived  state assignment 9 product term implementation 0 S0 S1 1 1 S0 S2 0 0 S1 S3 1 1 S1 S4 0 0 S2 S4 0 1 S2 S4 1 0 S3 S5 0 1 S3 S5 1 0 S4 S5 1 1 S4 S6 0 0 S5 S0 0 1 S5 S0 1 0 S6 S0 1 NOVA input file Implementation Strategies
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Xilinx FPGAs - 6 Espresso Inputs Espresso Outputs .i 4 .o 4 .ilb x q2 q1 q0 .ob d2 d1 d0 z .p 16 0 000 001 1 1 000 011 0 0 001 110 1 1 001 100 0 0 011 100 0 1 011 100 1 0 110 111 0 1 110 111 1 0 100 111 1 1 100 101 0 0 111 000 0 1 111 000 1 0 101 000 1 1 101 --- - 0 010 --- - 1 010 --- - .e .i 4 .o 4 .ilb x q2 q1 q0 .ob d2 d1 d0 z .p 9 0001 0100 10-0 0100 01-0 0100 1-1- 0001 -0-1 1000 0-0- 0001 -1-0 1000 --10 0100 ---0 0010 .e Implementation Strategies
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Xilinx FPGAs - 7 D2 = Q2 • Q0 + Q2 • Q0 D1 = X • Q2 • Q1 • Q0 + X • Q2 • Q0 + X • Q2 • Q0 + Q1 • Q0 D0 = Q0 Z = X• Q1 + X • Q1 175 X Q2 Q1 Q0 Z D2 D1 D0 converter PLA 1 0 CLK 1 0 1 \Reset CLK 13 12 X D C B A QD QD QC QC QB QB QA QA CLR 9 1 15 14 10 11 7 6 2 3 Z 5 4 Implementation Strategies
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Xilinx FPGAs - 8 10H8 PAL: 10 inputs, 8 outputs, 2 product terms per OR gate D1 = D11 + D12 D11 = X • Q2 • Q1 • Q0  +  X • Q2 • Q0 D12 = X • Q2 • Q0  +  Q1 • Q0 0. Q2 • Q0 1. Q2 • Q0 8. X • Q2 • Q1 • Q0 9. X • Q2 • Q0 16. X • Q2 • Q0 17. Q1 • Q0 24. D11 25. D12 32. Q0 33. not used 40. X • Q1 41. X • Q1 X Q2 Q1 Q0 D11 D12 D2 D11 D12 D1 D0 Z 0 1 2 3 4 5 8 9 12 13 16 17 20 21 24 25 28 29 30 31 0 1 8 9 16 17 24 25 32 33 40 41 Implementation Strategies
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Xilinx FPGAs - 9 X Q2 Q1
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This note was uploaded on 12/15/2010 for the course ECE 271 taught by Professor Garrisongreenwood during the Spring '10 term at Pohang University of Science and Technology.

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Lec-12-FPGAsa - ImplementationStrategies ROMbasedDesign

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