271_6_s - counter that you can build in a Spartan XCS30XL...

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ECE 271 Homework #6 1. (3 points) Briefly explain how the resources in a GAL architecture can be used to implement a FSM. The excitation equations and the output equations are implemented in the programmable AND-OR logic. The memory (storage) is implemented in the registers in the OLMC (output logic macro cells) 2. (3 points) Repeat question 1 for a FPGA The excitation equations and the output equations are implemented in LUTs. The storage is implemented in the registers assigned to each CLB. (The LUTs are in the CLBs as well.) 3. (2 point) Theoretically, what size is the largest modulo- n
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Unformatted text preview: counter that you can build in a Spartan XCS30XL FPGA? modulo-2 1152 4. (2 point) How many VCC pins are there on a Spartan XCS40 FPGA that comes in a BGA package? 27 5. (2 points) FPGAs are programmed from a compiled HDL description (i.e., a Verilog or VHDL program). What would you have to have in the HDL description to use the global set/reset function in the Spartan FPGA? To use this global net, place an input pad and input buffer in the HDL code, driving the GSR pin of the STARTUP symbol.icated inputs for these functions. (page 4-21 of application note on the Spartan FPGA)...
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This note was uploaded on 12/15/2010 for the course ECE 271 taught by Professor Garrisongreenwood during the Spring '10 term at Pohang University of Science and Technology.

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